Reflections on 10 Years as a Commercial On-chip Interconnect Provider

1. Reflections on 10 Years as a Commercial On-chip Interconnect Provider Drew WingardCTO, Sonics, Inc.

2. Agenda • The Market Opportunity • The Technology • The Business 10 Years as an Interconnect Provider (NOCS 2007)

3. Market Opportunity September 1996 • The Internet is hot • Yahoo/Netscape/etc. newly public • Silicon Valley VC’s looking for anything network-related • Convergence is hot • Want to mix data processing, communications, and content • Many of the new applications are consumer-driven • Very sensitive to cost and form factor • Integration is key • SoC’s seem like the only rational approach… 10 Years as an Interconnect Provider (NOCS 2007)

4. SONICS, INC. “Systemson ICs”

5. Current Trends • Digital Convergence • consumer, computer & communications • Moore’s Law continues • single chip systems • Architectural Convergence • General purpose CPU with hardware assist • Traditional design approaches failing • Traditional vendors cannot meet “time-to-market” demands or cost targets

6. The Battleground For Consumers Internet Consumer Electronics NC PC PDA Networks Computers

7. Systems-On-ICs: Applications • Consumer Electronics • Internet TV, Email Phones, DVD, Set-Top Box • Networking • Routers, Switches, Network Interface Devices • Communications • Wireless Phones, Wireless PDAs • Computing • Net Computers, PDAs

8. Examples of Reference Platforms

9. SONICS, INC. System Architectures Today Future Networking Consumer Info Appliance Communications

10. DRAM Processor Core SRAM Graphics Clocks Ethernet Interface Communications Sonics Integration Foundation On-chip I/O Modem Interface Audio Interface Other Processor DRAM Processor Core SRAM Graphics Clocks Silicon BackPlane Ethernet Interface Sonics Integration Foundation On-chip I/O Modem Interface Audio Interface Other Video Processor Core SRAM Memory Graphics Clocks Ethernet Interface Sonics Integration Foundation On-chip I/O Modem Interface Audio Interface Other Sonics Integration Architecture

11. Mission Statement SONICS will be a leading manufacturer of single-chip systems for networking & communications applications. OOPS!!!

12. Rethinking the Market Opportunity • Market needed high-function, inexpensive silicon to enable convergence applications • Sonics had a novel approach to address the integration challenges, but… • No OEM’s would trust these markets to a start-up • No VC would fund a “fabless, chipless” IC company! • “If our strategic value is in our ability to integrate, maybe we should package and license our integration technology…” 10 Years as an Interconnect Provider (NOCS 2007)

13. IC Designer Challenges • IC Designers become System Designers • Performance Modeling Across Design Hierarchy • Hardware/Software Partitioning and Co-design • Mix-and-Match IP • Validation/Test of Deeply-Embedded Systems • Predictable Physical Design The Sonics Integration Architecture is a systematic solution for these challenges

14. IC Designers become System Designers Integration Architecture • Time-to-market will drive the need for IC Designers to develop a systematic approach to: • scalability over a wide-range of applications • ready integration of proven IP with newly designed IP System House Product Specification IC Designer System Level Integration Semiconductor House IP Providers

15. Systems Software PLD ASSP Full Custom The Sonics Solution Sonics Integration Architecture Cores + Communications + Chips Silicon BackplaneLogic Backplane System Designer IC Designer System-Level Tools Core Developer Processor Display Memory Communications

16. Architectures Need Ecosystems Sonics Module Interface: Open Technology Product Support IP Provider EDA Software Sonics Architecture API: Open Technology OS Provider SONICS PLD System House ASIC ASSP Technology License - Up Front License Fee - Implementation - Royalty - Support Software Tools IPWorks License

17. The Business Opportunity: Summary • Since early 1997, Sonics has been a semiconductor IP supplier focused on selling interconnect networks for SoC applications • Fortunately, fully half of the $68 Billion market for digital logic semiconductors is now classified as “SoC” • … and the rest seems to be on its way! 10 Years as an Interconnect Provider (NOCS 2007)

18. The Technology • Since Sonics’ original intent was to integrate IP from lots of sources (including customers!), we’ve always had a strong focus on interfacing • Key elements of Sonics’ architecture (1997-now) • Flexible interface sockets • De-coupled agents offering data-flow services • Advanced internal fabrics • While all of the names – and much of the underlying technology – have changed, we’re still on that same course… 10 Years as an Interconnect Provider (NOCS 2007)

19. Flexible Sockets 10 Years as an Interconnect Provider (NOCS 2007)

20. IC Designers become System Designers Integration Architecture • Time-to-market will drive the need for IC Designers to develop a systematic approach to: • scalability over a wide-range of applications • ready integration of proven IP with newly designed IP System House Product Specification IC Designer System Level Integration Semiconductor House IP Providers

21. VSIA On-Chip Bus WG Background • Sonics Module Interface is a Virtual Component Interface specifically designed to: • Isolate VC’s from logical and physical bus requirements (i.e be a bus wrapper) • Specify both basic and advanced functionality • Minimize area overhead for simple VC’s • Improve performance for complex VC’s • Provide structure for user-defined enhancements • Allow “black box” verification and testing • Interface should be symmetric, so VC’s can also connect directly to each other (i.e. without an on-chip bus)

22. VSIA Model and Sonics Integration Architecture VSIA On-chip Bus Model Sonics Integration Architecture Virtual Component Bus Wrapper Transaction Protocol Sonics Module Interface Bus Transfer Protocol Silicon Backplane Protocol Physical Bus Physical Bus The Sonics Silicon Backplane is a proprietary communication protocol that facilitates connection of VC cores with widely-varying performance requirements

23. Master Master Master Master Slave Slave Slave Slave Sonics Module Interface Virtual Component Virtual Component Virtual Component Module Interface Response Request Initiator Target On-Chip Bus

24. Additions: Threads • A thread is a sequence of transfers that must occur in-order with respect to one another • Transfers in different threads may occur out-of-order • Threads can represent: • Separate, independent streams • Separate operation types • Combinations of the above • Thread Identifiers are Layer 2 (Point-to-point) • Additional signals to support threads • Master passes ReqThreadID as tag with request ( 4 bits) • Slave returns RespThreadID with response • Optional ThreadBusy bit vectors for thread status Non-blockingflow control

25. Test Bench Example • Perl-based assembler / disassembler • Behavioral Verilog VC cores • Protocol checker at interface Transaction-basedverification ConnID ThreadID Cmd Addr (Length) (Data) 0x1F 0x2 bfill32 0x1000 8 0x12345678 0x1F 0x2 bread32 0x1FFF 8 0x10 0x1 read8 0x8 0x10 0x1 write8 0x2008 0xFF

26. Conclusions • Wide adoption of any standardized VC interface depends on two technical measures • Area efficiency for simple/low-performance VC’s • Performance capability for complex/high-performance VC’s • Sonics Module Interface defines: • Small core of mandatory signals • Wide range of optional signals • Structure method for extension • Logical and electrical protocols • Necessary for validation • Allows true “black box” VC-based design and testing Highlyconfigurable

27. What happened to SMI? • Re-christened “Open Core Protocol” in 1999 • OCP-IP announced 2001 • Original GSC: MIPS, Nokia, Sonics, TI, UMC • Currently over 170 members • Basic OCP protocol is the same as SMI • OCP 2.0 added significant improvements to burst model 10 Years as an Interconnect Provider (NOCS 2007)

28. Agents and Fabrics • Sonics’ interconnects have always been highly configurable • Originally based on intuition about required flexibility • Now based on customer demand • Biggest input into configuration decision is based on chip-level data flow 10 Years as an Interconnect Provider (NOCS 2007)

29. System-on-a-Chip Communications IP Core Communications Bandwidth Performance-Driven CPU PCI Real-Time 3D DSP Video/2D ATM P1394 LAN 4M 16M 64M 256M 1G 4G 16G 64G 256G Bandwidth (bits/sec) Characteristics: • Wide performance range • Increasing real-time multimedia/networking traffic • Shared memory requirements • Complex interactions • Challenging Design

30. DMA CPU DSP DMA CPU DSP A System Bus Sonics Silicon Backplane A Bridge C B I O O B Peripheral Bus C I O O Sonics Module Interface Custom Interfaces Sonics Integration Architecture Conventional Sonics Integration Architecture Allows unification of all on-chip communication

31. DMA CPU DSP A C MEM I O Silicon Backplane Sonics Module Interface Initiator Module Target Module Logic Backplane Bridge Integration Architecture Aspects* • Tunable Communications Subsystems • Silicon BackplaneTM • Logic BackplaneTM • Configurable IP Core Interface • Sonics Module Interface • Design Software • Backplane Compiler * Patent Pending Agents

32. SOC Data Flow DMA CPU DSP A C MEM I O O < 10 Mbits/sec < 100 Mbits/sec > 100 Mbits/sec Bus Bandwidth Requirements • Must satisfy sum of sustained BW • Total bus BW >peak BW of any IP Core • Bandwidth mismatch between Bus and IP Cores • Need de-coupled Bus performance Except DRAM

33. Transmit FIFO Receive FIFO IP Core IP Core Arbiter Address Computer Bus Data       IP Core IP Core Time Computer Bus Approach

34. Transmit FIFO Receive FIFO IP Core IP Core TDMA TDMA Communications Bus Data       IP Core IP Core Time Communication Bus Approach

35. Arbitration Command Guaranteed Bandwidth Arbitration • Independent arbitration for every cycle • Two phases • Distributed TDMA • Round robin • Gives SOC designer fine control oversystem bandwidth Current Slot

36. Pipeline Diagram OOPS!!!

37. Command Response FlagNum Flag[7] RD1 RD1 RTRY Valid 7 Integrated Signaling Mechanism • Dedicated Backplane wires (Flags) support: • Bus-style Out-of-Band Signaling (Interrupts) • Point-to-Point Communications (Flow control) • Dynamic point-to-point (Retry mechanism) • Integral part of Integration Architecture • Same design flow, timing, flexibility as address/data part • Retry Mechanism:

38. Silicon Backplane Interface Clock C L O C K Address/Data Flow Address Decoder Address / Control Configuration Registers Data Synchronizer (Optional)  Sonics Module Interface Target Module Block Diagram

39. Bandwidth Engineering Define System Specifications Analyze Performance System Bandwidth & Latency Constraints Partition System soccomp IP Core Requirements Select / Design IP Cores Backplane Compiler IP Cores Silicon Backplane Simulate / Integrate SOC

40. MicroNetwork Definition Network: A heterogeneous integrated network that unifies, decouples, and manages all of the communication between processors, memories, and input/output devices

41. SOC Integration Flow • Pre-characterize the MicroNetwork physical design • Determine base architecture • Choose MicroNetwork data flow parameters • Build SOC data flow model (behavioral + traces) • Improve the model • Test the physical design • Integrate actual IP Cores and verify functionality • Map the control flow • Verify system functionality • Map manufacturing test and complete physical design

42. IP Core Integration

43. IP Core Integration

44. IP Core Integration

45. IP Core Integration

46. Configuring MicroNetwork Parameters Select Address Map Choose Data Width & Pipeline Depth Configure Arbitration

47. Today’s Sonics Technology 10 Years as an Interconnect Provider (NOCS 2007)

48. 16 128 CPU DMA DRAM Controller Master Slave Master Slave Core Function Core Function Core Function Communication Communication Communication Socket Agent BusAdapter BusAdapter Agent BusAdapter Agent BusAdapter Agent Slave Slave Master Master Internal Fabric SMART Interconnect Network-based SoC: Active Decoupling • Separation • Abstraction • Optimization • Independence DMA DRAM Controller CPU Network 10 Years as an Interconnect Provider (NOCS 2007)

49. The Intelligence is in the Agents INITIATOR SOCKETS • Agents provide… • Protocol conversion • Agent adapts to IP core • Decoupling of IP cores from fabric • Provide local, isolated environment • Layered services • Agent services • Power management • Security management • Error management • QoS • Burst, width, and command conversion I I I I I Initiator Agents (IA) Fabric Target Agents (TA) T T T T T TARGET SOCKETS 10 Years as an Interconnect Provider (NOCS 2007)

50. Other approaches Full Support Partial Support Global Interconnect Responsibilities • Routing • Getting requests, responses and data to the desired destination • Access control • Managing contention for shared resources (ensuring QoS) • Ensuring requested access is allowed (security and protection) • Error management • Detection, reporting, and SW recovery support • Power management • Activity detection, clock and voltage removal support • Connectivity • Protocol conversion • Data width / clock frequency conversion • Spanning distance • Connecting endpoints at required frequency and latency 10 Years as an Interconnect Provider (NOCS 2007)