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System on a Programmable Chip (System on a Reprogrammable Chip)

System on a Programmable Chip (System on a Reprogrammable Chip). SoC. SoC: A chip that integrates the major functional elements of a complete end product. Complex FPGAs : CPU Memory Arithmetic units (multipliers, …) Peripheral modules Logic  Whole system on a chip. Peripherals.

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System on a Programmable Chip (System on a Reprogrammable Chip)

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  1. System on a Programmable Chip(System on a Reprogrammable Chip)

  2. SoC • SoC: • A chip that integrates the major functional elements of a complete end product. • Complex FPGAs : • CPU • Memory • Arithmetic units (multipliers, …) • Peripheral modules • Logic  Whole system on a chip

  3. Peripherals • In programmable devices, the flexibility can be used to modify the • interconnection infrastructure according to the type of application to be implemented. • each application can first be analysed to derive and implement the best communication infrastructure for its computation. • Despite the great interest in network on chip in the last couple of years, interconnection on chip is dominated by the SoC communication paradigm which is in most of the case bus-based. Leading existing solutions were previously developed for SoCs before adapted to SoPCs. • Two bus systems in SoPC era: • CoreConnect from IBM and • ARM AMBA.

  4. System integration with CoreConnect buses

  5. IBM CoreConnect • Busses: • PLB: a high-performance bus, used to connect high-bandwidth devices such as high-performance processor cores, external memory interfaces and DMA controllers. • OPB: a secondary bus that can be used to decouple the peripherals from the PLB to avoid a lost of system performance. • Peripherals such as serial ports, parallel ports, UARTs, GPIO, timers and other low bandwidth devices should be attached to the OPB. • Access to the peripherals on the OPB bus by PLB masters is done through a bridge. • Bridge: • to allow for communication to happen between two modules attached on the two different busses. • used as a slave device on the PLB and as master on the OPB. • performs dynamic bus sizing, to allow devices with different data widths to communicate. • DCR: • to allow lower performance status and configuration registers to be read and written. • a fully synchronous bus that provides a maximum throughput of one read or write transfer every two cycles. • removes configuration registers from the memory address map, reduces loading and improves bandwidth of the processor local bus.

  6. two different buses: • Other connections: • Besides those two buses, several possibilities exist to directly connect the component. Dedicated lines or crossbar switches can be used,

  7. References • [Bobda07] Christophe Bobda, “Introduction to Reconfigurable Computing: Architectures, Algorithms and Applications,” Springer, 2007. • [SORC] “Xilinx Design Reuse Methodology for ASIC and FPGA Designers SYSTEM-ON-A-CHIP DESIGNS REUSE SOLUTIONS

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