An FPGA Wire Database for Run-Time Routers

1. An FPGA Wire Database for Run-Time Routers Eric Keller Scott McMillan

2. Requirements • Low-Memory Overhead • Embedded system have limited resources • Low-Level • Run-time applications require tight control of routes • Incremental • Run-time applications need to add and remove a few nets at a time

3. Background • JBits is a Java API that provides direct access to resources in a Xilinx FPGA bitstream • e.g. LUTs, routing resources, BRAMs, ... • Supports run-time reconfiguration • Modify and reconfigure device programmatically • Run-time tools have been built on top of JBits • JRoute (run-time router), VirtexDS (simulator), BoardScope (debugger), etc.

4. Definitions • Wire – A template of a physical wire tied to a type of tile. Includes mux input and output connectivity information (intra-tile routing graph). • Pin – An instantiation of a Wire template that is specific to a tile in the device (includes tile coordinates). • Segment – A collection of Pins that are directly connected together across tiles (inter-tile routing graph).

5. Definitions • Example: SingleEast line • Note: Wire template name comes from output of multiplexer.

6. Intra-Tile Routing Graph • Xilinx FPGAs are organized into tiles • e.g. CLB, BRAM, IOB A B A A A B A A A B A A • Within a tile there is connectivity information about each routing resource • Same for all tiles of the same type

7. Intra-Tile Routing Graph • Wire template provides methods to get sources (input connections), get sinks (output connections) and create a connection. Wire getSink(int i) - gets the ith possible sink Wire getSource(int i) - gets the ith possible source void connectSource(int i, int row, int col) - set the bits that connects the ith source to this wire. The row and col are needed because the Wire object is not specific to a tile location H6E0 Sources x x Sinks "Bits"

8. Advantages of Intra-Tile Routing Graph • Store connectivity information only once for each tile type (Not once for every tile on device) • Device independent (still architecture dependent) • Greedy loading of wire template classes (only load wires that are used) • In implementation of Smith-Watermann algorithm only 1,136 out of 2,424 wires will be instantiated

9. Inter-Tile Routing Graph • Segments are built at run-time with software • Reduces storage by not having device specific flat routing graphs • A Segment is a set of pins that are directly connected

10. Inter-Tile Routing Graph • Wire templates provide an abstract method to get its attached segment (inter-tile graph) at run-time • Wire.getSegment(int row, int col) • Segment generated for each wire depends on tile location (e.g. Hex line will have different segment when located in the middle of the device versus on the edge). • Segment generation requires extra CPU cycles • Segments can be cached for improved performance

11. Example Code // Prints every pin on segment and all sinks of that pin Wire wire = com.xilinx.JBits.Virtex.Bits.Wires.Center.E0.getWire(); Segment seg = wire.getSegment(row, col); for (i=0;i<seg.numPins();i++) { Pin p = seg.get(i); System.out.println(“Pin: “ + p); w = lookup.getWire(p); // gets the tile specific version of the wire for (int j=0; j<w.numSinks(); j++) { sink = w.getSink(j); System.out.println(“ sink: “ + sink); } }

12. Defect Testing • Problem: Isolate defective wires on FPGA • Requires ability to specify individual wires • Route from an output to a wire then from that wire to an input • Route using a fully specified net (i.e. every wire in the net is specified by the user) • The Wire database supports both

13. Defect Tolerance • Problem: After isolating fault, need to be able to route around it • Each Pin can be specified with its Wire ID and tile coordinates • JRoute (JBits run-time router) has the ability to avoid faulty Pins by marking them as used

14. Reconfigurable CAM • CAM (Content Addressable Memory) • Give it the content and it will give you the address • Used in routers • Use JRoute to modify the priority encoder • Incrementally add/remove nets • Order in priority encoder determines priority • Reroute nets from the match unit to the priority encoder match unit priority encoder

15. Debugging • Observe internal signals by instrumenting design with extra logic • Internal Logic Analyzer • Route signal to IOB and use external logic analyzer • With run-time routing a user can modify which nets are being observed

16. RTP Cores • Run-Time Parameterizable Cores • Modify design at run time using high level cores • Need to be able to connect/disconnect cores • Run-time routing performs the dynamic modification of the connectivity

17. Task Swapping • Problem: Need the ability to swap in/out modules • Static router restricts routes from going through modules (constrains routes to the module area) • Dynamic router can connect up module interfaces and avoid existing static routes

18. Conclusions • JBits Wire Database provides: • Low-level control • Incremental addition/removal of nets • More efficient memory usage for embedded applications • A wire database written in Java uses an object oriented approach to the routing graph • Segments are built at run-time using abstract interfaces