DCS M onitoring and Safety for Strip Upgrade

1. DCS Monitoring and Safety for Strip Upgrade D. Ferrère, University of Geneva ITK-Module Aug 31st , 2011 Why the DCS is investigated now? The service reduction and the increase in detector surface (vs SCT) require to think of using DCS at the FE level The earlier the DCS part is implemented the better it is for debugging and optimizing the future version • NB: • It is proposed to use an DCS architecture quite close to the current SCT • Barrel and EC should target for the same architecture • So far modularity is considered different • The powering scheme will have an impact on some part of the DCS architecture

2. Proposed DCS Overview Scheme Option 2 Option 1 LAN SCT DCS SCT DAQ CAN Bus CAN Bus Matrix CAN Bus Global Interlock Elmb Elmb ROD Ibox BOC BBIM 5 GB/s optical link TTC - DCS SPI or I2C bus DCS Type 2 cables PS Crate SMC Hybrid Environmental (Super-Module) Env. Structure Cooling Temp NTC Hybrid Temp RH • If DC-DC: local En/Dis • If SP: Vglobalto be controlled Hybrid Power Channel Interlock Detector RH PS Type 2  Type 4 cables 2

3. Proposal as of Today & Comments • What is proposed: • Most of the DCS diagnostics should go via the Optical link with FE & GBT-SCA • Environmental should still go to ELMB’ with individual lines (Possibly via SMC/EoS) • The cooling interlock (highest level) should still go to Ibox’ • The Module interlock will depend of the powering scheme and is steered locally for DC-DC or at the off-detector for the SP • It is optionally proposed to have a SMC/EoS interlock but at least a monitoring line • PS monitoring and state could be part of the diagnostic tool and via optical link but still have to be monitored at SMC/EoS and also at the PS crate • DCS hardware should be inside the counting room and it is proposed to avoid having iteminside the cavern. • NB: • DC-DC module interlock could be steered locally by a Latch integrated into HCC provided that the HCC is not supplied by the local DC-DC. Otherwise it has to be at the GBT-SCA level. • SP module interlock (via the shunt) should be sent from the Vglobal. GBT-SCA should send a coded information to control Vglobal! • It is not yet known where the opto-components will be located: on the SMC/EoS or somewhere else. If somewhere else which DCS to monitor and secure? • To investigate: • Latch mechanism based on temperature level to be implemented inside the HCC and to En/Dis local DC-DC • Latch mechanism based on temperature level to be implemented inside GBT-SCA to En/Dis local DC-DC. In case of SP it will require and information to be sent externally via optical link to the control the shunts. • Diagnostic like power and temperature implemented in the FE and HCC 3

4. DCS and Readout Data streams DCS DCS DCS DCS chain should be considered already at the chip level! DCS diagnostics desired rate at low frequency or on request DCS on SPI/LVDS from/to other SMC (Option 2) DCS for module interlock Module temp ABCn TTC Data/DCS HCC_1 TTC Data/DCS stream 1 SMC TTC/DCS stream (Option 1/3) DCS DCS GBT TTC Data/DCS stream 2 ABCn TTC Data/DCS HCC_2 TTC Data/DCS stream 24 Direct DCS DCS 5 Gbps 160 Mbps 4

5. DCS Overview Functions versus Cooling and Power Option 3 Can run without cooling but for limited time? Independent from cooling and PS Need cooling – low power Independent from cooling but need PS enable or DCS power Need cooling – High power 5

6. Stave Hybrid Supply and Control versus Powering Scheme Serial Powering Hybrid N+1 Hybrid N-1 Hybrid N FE EoS/SMC FE FE HCC HCC HCC VSC Vref-N-1 Vref-N Vref SPi SPi SPi VStave DGND VGlobal Where the low frequency signal is generated? Counting room is mainly considered Hybrid N+1 Hybrid N-1 DC-DC Hybrid N EoS/SMC Opto HCC HCC HCC FE FE FE GBT DC-DC Plug-in DC-DC Plug-in DC-DC Plug-in DCS 2.5V DC-DC Stage 2.5V 12V Do we need control or monitoring from DCS chip? DC-DC has to be locally controlled by HCC In both cases it is proposed to used the power control for module interlock! 6

7. DC-DC control and module interlock in SM prototype today H0 temp Comparators H1 temp 1-wire 8 switchable channels Operation allows individual hybrid power control and a safety interlock based on Hyb temp • NB: • This schematic is working and under operation with the SM prototype • Today the ADC is on the SMB but in a final scheme it should be implemented into HCC • In order to improve one should use: • Schmitt trigger after each comparator • A latch (1 state + RST) in order to have a full control on the operation 7

8. Module safety interlock for SP • Option 1: Power OFF the all SP chain when any temp of the hybrid chain exceed a threshold • Option 2: Power down the individual hybrid by acting on the shunt using Vglobal . It requires to deliver a coded interlock with hybrid address. 16 input channels FSM The option for this would be to implement the relevant features into a EoS Slow Control chip  GBT-SCA should be considered D. Ferrère & A. Marchioro Analog Mux Temp Limits adcin1 Requires at least 24 inputs 16 ADC results 12 to SCA internal bus 10 bit ADC Alarm Flag/Interlock or coded with address adcin16 Input Select ADC precision: 10 bit  precision ~…0.1-0.25°C Clock: 40MHz (possibly less) Number of input channels: 16 but 24 needed for short-strip stave? 32 channel option is still opened! Alarm flag signal: To be used for stave-module PS inhibit (LV & HV for serial powering) Minimum time for alarm flag @ 40 MHz (1024x25nsx16)  ~0.41 ms ASIC package size: Possible size of the GBT-SCA ~ 12x12mm2 8

9. Powering Conditions versus Hybrid Interlock Serial Powering Stave controller chips DCS + Shunt Control are vital - Power control & Temp interlock 1 for all the SP chain DC-DC HCC DCS is vital - Power control & Temp interlock 1 per hybrid 9

10. DCS Data & Interlock versus the Construction Phase & Test NB: Modules are never tested un-cooled either individually or on the stave 10

11. Summary and what next? • The DCS architecture for the strip Upgrade has been proposed since some time now • The main proposed change is to have more diagnostic tools and some DCS data running through the FE and the optical link via GBT • Safety interlock levels are proposed for: cooling loop, module, and EoS/SMC • The module interlock schematic is different depending of the powering scheme to be used • It seems essential that the DCS at the FE and HCC level are already implemented in the design for the next submission • It is essential that the strip requirements for GBT-SCA are soon written and ready for implementation in a first chip version (when?) • Need to agree: • Number of ADC channel and precision in the FE • Number of ADC channel and precision in the HCC + implementation of the mechanism for module interlock and En/Dis DC-DC • Module interlock baseline for the SP? • Requirements for GBT-SCA 11