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System-on-Chip (SoC) Testing: Present Solutions

System-on-Chip (SoC) Testing: Present Solutions. Pedram A. Riahi Prof. Z. Navabi Prof. F. Lombardi Prof. M. Tahoori. Northeastern University - Electrical and Computer Engineering Department. Contents. Embedded Core Peripheral Access Macro Testability IEEE P1500 Built-in Self-Test (BIST)

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System-on-Chip (SoC) Testing: Present Solutions

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  1. System-on-Chip (SoC) Testing: Present Solutions Pedram A. Riahi Prof. Z. Navabi Prof. F. Lombardi Prof. M. Tahoori Northeastern University - Electrical and Computer Engineering Department

  2. Contents • Embedded Core Peripheral Access • Macro Testability • IEEE P1500 • Built-in Self-Test (BIST) • Test Wrapper • Hybrid Solution Test Seminar

  3. Embedded Core Peripheral Access • Parallel Direct Access • Serial Direct Access • Functional Access • Test Integration for Core-based Systems Test Seminar

  4. Macro Testability • Full Scan / Boundary Scan • Full Scan / BIST / Boundary Scan • Full Scan / Test Bus • Test Bus / Boundary Scan Chain • Partial Netlist / Partial Boundary Scan • Binary Decision Diagram • Core Transparency Test Seminar

  5. Macro Testability Full Scan / Boundary Scan • (FScan-BScan) Test Seminar

  6. Macro Testability Full Scan / Boundary Scan • Full Isolation • Partial Isolation Test Seminar

  7. Macro Testability Full Scan / BIST / Boundary Scan Test Seminar

  8. Macro Testability Binary Decision Diagram (BDD) Test Seminar

  9. Macro Testability Core Transparency • FPath • H-Scan Test Seminar

  10. Macro Testability Other Methods • Full Scan / Test Bus (FScan/TBus) • Test Bus / Boundary Scan Chain • Partial Netlist / Partial Boundary Scan Test Seminar

  11. IEEE P1500 • Core Test Language (CTL) • Cores Without Boundary Scan • Cores with Boundary Scan Test Seminar

  12. IEEE P1500 Cores Without Boundary Scan • General Architecture • Input Cell • Output Cell • Control Scan Path (Under Discussion) Test Seminar

  13. IEEE P1500 Cores With Boundary Scan Test Seminar

  14. Built-In Self-Test (BIST) Test Seminar

  15. Test Wrapper • Registered Isolation • Slice Isolation, Slice Isolation Cell • Core DFT Interface Test Seminar

  16. Test Wrapper Registered Isolation Test Seminar

  17. Test Wrapper Slice Isolation Test Seminar

  18. Test Wrapper Core DFT Interface Test Seminar

  19. Hybrid Solution • Internal Parallel Scan • Wrapper Parallel Scan • Embedded Memory BIST • Other DFT Features Test Seminar

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