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Embedded Architectures: Configurable, Re-configurable, or what?

viewgraph downloading, for a link see: http://hartenstein.de. Grenoble, France October 8 - 11 2002. Embedded Architectures: Configurable, Re-configurable, or what? . Re-configurable ! . (position statements) Reiner Hartenstein University of Kaiserslautern.

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Embedded Architectures: Configurable, Re-configurable, or what?

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  1. viewgraph downloading, for a link see: http://hartenstein.de Grenoble, France October 8 - 11 2002 Embedded Architectures: Configurable, Re-configurable, or what? Re-configurable ! (position statements) Reiner Hartenstein University of Kaiserslautern Pierre Paulin, STMicro (moderator); Henk Corporaal, IMEC; Reiner Hartenstein, University of Kaiserslautern; Oz Levia, Improv Systems; Marco Pavesi, Italtel; Chris Rowen, Tensilica. Thursday, Oct 10, session 5, 4.00 - 5.00 p.m.

  2. „Re-configurable Hardware“ ?? Terminology has been highly confusing „Re-configurable Hardware“ ?? this „Hardware“ is not hard ! it‘s Morphware We need a concise terminology: a consensus is on the way 2

  3. DPA (r) (r) DPU DPU DPU CPU instruction sequencer Terminology: DPU versus CPU ... • DPU: data path unit • DPA: DPU array • GA: gate array • rDPU: reconfigurable DPU • rDPA: reconfigurable DPA • rGA: reconfigurable GA • DPU is no CPU: there is nothing central - like in a DPA 3

  4. Digital System Platforms clearly distinguished 4

  5. time input data streams DPA x x x x ... which data item at which time at which port x x x x time port # | x | | time - - - x x x - - - - x x x x x x x x x - - - - - x x x - | | | x x x - - | | | port # | | | port # x | | | x x | | x x x output data streams x x x time flowware defines .... flowware manipulates the data counter(s) ... ... software manipulates the program counter 5

  6. high level source program wrapper data streams intermediate M M M M mapper rDPA M M configware scheduler r. Data Path Array M M M M M M M M M M flowware address generator Configware / Flowware Compilation data sequencer 6

  7. most important contributor to nano SoC we need rDPAs for: • cellular wireless • multimedia • other applications relative merits: • performance • flexibility • time to market • product longevity key functionalities: to cope with • compute requirements • unstable standards • multiple standards 7

  8. 4G 3G Memory (Moore’s Law) 100 000 000 10 000 000 1000 000 100 000 10 000 1000 100 10 1 2G wireless microprocessor / DSP Algorithmic Complexity (Shannon’s Law) 1G Transistors/chip Normalized processor speed 1960 1970 1980 1990 2000 2010 Processor Performance Normalized processor speed 8

  9. rDPAs go far beyond bridging the gap *) R. Hartenstein: ISIS 1997 throughput von Neumann hard- wired hardwired rDPAs (reconfigurable computing)* FPGA rDPA 2 1 0.5 0.25 0.13 0.1 0,07 DSP Reconfigurable logic instruction set processors flexibility standard microprocessor Performance vs. Flexibility DeMan [T. Claasen et al.: ISSCC 1999] MOPS / mW 1000 100 10 1 0.1 0.01 0.001 µ feature size 9

  10. cSoC for wireless communication et al. incremental dynamic reconfiguration Xtreme processing unit (XPU) from PACT rDPA http://pactcorp.com Layout for UMC 0.13 mm CMOS 10

  11. Revenue / month reconfigurable Product [Tom Kean] Update 2 with Update 1 download Product ASIC Product Time / months 1 10 20 30 Time to Market • A Fundamental Paradigm Shift in Silicon Application 11

  12. University of Kaiserslautern © 2001,reiner@hartenstein.de http://KressArray.de >>> END END 12

  13. University of Kaiserslautern © 2001,reiner@hartenstein.de http://KressArray.de >>> Appendix Appendix for discussion 13

  14. vN bottleneck caches, ... CPU stolen from Bob Colwell Why a dichotomy of machine paradigms? vN: unbalanced • data stream machine: • bad message: caches do not help • good message: no vN bottleneck • caches not needed 14

  15. Software Configware S/W S/W ROM, Flash eFPGA Standard I/O blocks Config. DSP S/W S/W S/W Config. MCU Processor eSRAM eDRAM eFPGA FPGA Scalable SoC interconnect Mem C/W C/W C/W ASIC ASIP RISC, VLIW microProg peripherals RISC, VLIW Config. DSP Gen. Purp. RISC, VLIW rDPA RC C/W *) System on a programmable Chip Soap Chip* Platform Template important: coarse grain morphware Standard H/W IP ©2002,reiner@hartenstein.de 15 http://hartenstein.de

  16. Anti machine data stream machine Programming sources von Neumann instruction stream machine hardwired only reconfigurable or hardwired flowware 16

  17. data-stream machine Flowware Software Configware embedded memory architecture* Machine paradigms von Neumann instruction stream machine 17

  18. design cost product life cycle year Cost new business model needed the key enabler: morphware 18

  19. approaching consensus Glossary digital system platforms: DPU data path unit rDPU reconfigurable DPU DPA data path array (DPU array) rDPA reconfigurable DPA ISP instruction set processor AM anti machine AMP data stream processor* rAMP reconfigurable AMP *) no “dataflow machine” categories of morphware: **) instruction set processor *) data stream processor 19

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