Text book

1. TNE064Digital Communication ElectronicsQin-Zhong YeITNLinköping Universityemail: qin-zhong.ye@liu.sehttp://www.itn.liu.se/~qinye/dce Digital Kommunikationselektronik TNE064 Lecture 1

2. Text book U. Meyer-Baese Digital Signal Processing with Field Programmable Gate Arrays Second Edition or Third Edition Springer Digital Kommunikationselektronik TNE064 Lecture 1

3. Digital Signal Porcessing and Digital Communication Systems • Introduction (Chapter 1) • Computer Arithmetic (Chapter 2) • Finite Impulse Response (FIR) Digital Filter (Chapter 3) • Fouier Transforms (Chapter 6) • Error Control and Cryptography (Chapter 7.2) • WLAN and Bluetooth Digital Kommunikationselektronik TNE064 Lecture 1

4. Introduction • Overview of Digital Signal Processing (DSP) • FPGA Technology • DSP Technology Requirements • Design Implementation • VHDL Digital Kommunikationselektronik TNE064 Lecture 1

5. Digital Kommunikationselektronik TNE064 Lecture 1

6. Typical DSP Application Digital Kommunikationselektronik TNE064 Lecture 1

7. Classification of VLSI Circuits Digital Kommunikationselektronik TNE064 Lecture 1

8. Custom Chips, Standard Cells, and Gate Arrays • Custom Chips • Largest number of logic gates • Highest speed • Designer may create any layout. • Large design effort • Long development time • Large production quantity is required. Digital Kommunikationselektronik TNE064 Lecture 1

9. Standard Cells • Often called Application-Specific Integrated Circuits (ASICs) • The layout of individual gates (standard cells) is predesigned and stored in a library. • The chip layout can be created automatically by CAD tools because of the regular arrangement of logic gates (cells) in rows. Digital Kommunikationselektronik TNE064 Lecture 1

10. A section of two rows in a standard-cell chip Digital Kommunikationselektronik TNE064 Lecture 1

11. Gate Arrays • Transistor layers on the silicon wafer are first fabricated to produce a gate-array template. • Connecting wires are then fabricated on the template to produce a user´s circuit. • The technology is also known as a sea-of-gates technology. Digital Kommunikationselektronik TNE064 Lecture 1

12. A sea-of-gates gate array Digital Kommunikationselektronik TNE064 Lecture 1

13. An example of a logic function in a gate array Digital Kommunikationselektronik TNE064 Lecture 1

14. 1 2 n Input buffers and inverters x x x x 1 n 1 n P 1 OR plane AND plane P k f f 1 m • Programmable Logic Array (PLA) • A collection of AND gates that feeds a set of OR gates • The inputs to each gate are programmable. General structure of a PLA Digital Kommunikationselektronik TNE064 Lecture 1

15. x x x 1 2 3 Programmable connections OR plane P 1 P 2 P 3 P 4 AND plane Gate-level diagram of a PLA f f 1 2 Digital Kommunikationselektronik TNE064 Lecture 1

16. x x x 1 2 3 OR plane P 1 P 2 P 3 P 4 AND plane Customary schematic of a PLA f f 1 2 Digital Kommunikationselektronik TNE064 Lecture 1

17. x x x 1 2 3 P 1 f 1 P 2 P 3 f 2 P 4 AND plane • Programmable Array Logic (PAL) • The AND gates are programmable, but the OR gates are fixed. An example of a PAL Digital Kommunikationselektronik TNE064 Lecture 1

18. Macrocell Select Enable f 1 Flip-flop D Q Clock To AND plane Output circuitry Digital Kommunikationselektronik TNE064 Lecture 1

19. Complex Programmable Logic Devices (CPLD) • Multiple blocks of sum-of-product logic circuits (PAL-like blocks) • Internal wiring resources (interconnection wires) to connect the circuit blocks • I/O blocks • In-System Programming (ISP) with JTAG port • Nonvolatile programming Digital Kommunikationselektronik TNE064 Lecture 1

20. I/O block PAL-like PAL-like I/O block block block Interconnection wires I/O block PAL-like PAL-like I/O block block block Structure of a CPLD Digital Kommunikationselektronik TNE064 Lecture 1

21. A section of a CPLD Digital Kommunikationselektronik TNE064 Lecture 1

22. Field-Programmable Gate Arrays (FPGA) • An array of logic blocks • Each logic block typically has a small number of inputs and one output. • FPGA products have different types of logic blocks. • Interconnection wires and switches (routing channels) • I/O blocks • In-System Programming (ISP) with JTAG port • Storage cells are volatile. Digital Kommunikationselektronik TNE064 Lecture 1

23. Logic block Interconnection switches I/O block I/O block I/O block I/O block Structure of an FPGA Digital Kommunikationselektronik TNE064 Lecture 1

24. Lookup table LUTs usually have 4 to 6 inputs (16 to 64 storage cells). A two-input lookup table Digital Kommunikationselektronik TNE064 Lecture 1

25. Inclusion of a flip-flop with a LUT Digital Kommunikationselektronik TNE064 Lecture 1

26. A section of a programmed FPGA Digital Kommunikationselektronik TNE064 Lecture 1

27. FPGA Structure • Small look-up tables (LUT) • Xilinx XC4000: Eech Configurable Logic Block (CLB) has 2 separate 4-input 1-output LUTs. Each CLB can be used as 16x2- or 32x1-bit RAM or ROM. • Altera Flex 10K: Each Logic Element (LE) consists of a flip-flop, a 4-input 1-output LUT or 3-input 1-output LUT and a fast-carry logic. • Large RAM blocks: Embedded Array Blocks (EABs), e.g., 2-kbit RAM Digital Kommunikationselektronik TNE064 Lecture 1

28. FPL technology Digital Kommunikationselektronik TNE064 Lecture 1

29. Advantages of FPLDcompared with ASIC • A reduction in development time (rapid propotyping) by 3 to 4 • In-circuit reprogrammability • Lower NRE costs resulting in more ecomomical designs for solutions requiring less than 1000 units Digital Kommunikationselektronik TNE064 Lecture 1

30. Comparison of PDSP and FPGA • Programmable Digital Signal Processors (PDSPs) • RISC architecture • Multiply and accumulate (MAC) unit with a multistage pipeline architecture • Suitable for algorithms using MAC • FPGA • Suitable for high throughput applications • Suitable for front-end applications (e.g., FIR filters, CORDIC algorithms, FFTs) Digital Kommunikationselektronik TNE064 Lecture 1

31. Computer Arithmetic • Number Representation See Fig. 2.1. • Fixed-point numbers • Unsigned integer • Signed magnitude (SM) • Two’s compliment (2C) • One’s compliment (1C) • Diminished one system (D1) • Bias system Digital Kommunikationselektronik TNE064 Lecture 1

32. Unconventional fixed-point numbers • Signed digit numbers (SD) • SD is not unique. • Canonic signed digit system (CSD) • With minimum number of none-zero elements • Classical CSD coding algorithm Starting with the LSB substitute all 1 sequences equal or larger than two with 10…01. • Classical CSD has at least one zero between two digits which may have values 1 or 1. • Carry-free Addition Digital Kommunikationselektronik TNE064 Lecture 1

33. Multiplication with a constant coefficient • Multiplier Adder Graph (MAG) • Factor the coefficient into several factors and realize the individual factors in an optimal CSD sense. One adder: A = 2k0 (2k1± 2k2) Two adders: A = 2k0 (2k1± 2k2 ± 2k3) A = 2k0 (2k1± 2k2) (2k3± 2k4) Three adders: A = 2k0 (2k1± 2k2 ± 2k3 ± 2k4) . . See Fig. 2.2 and Fig. 2.3. Digital Kommunikationselektronik TNE064 Lecture 1

34. Logarithmic Number System (LNS) • Fixed mantissa (system’s radix) • Fractional exponent x = ± r ±ex • Efficient implementation of multiplication, division, square-rooting, or squaring. • Addition and subtraction require look-up tables. Digital Kommunikationselektronik TNE064 Lecture 1

35. Residue Number System (RNS) • RNS is defined with respect to a positive integer basis set {m1, m2, …, mL}, where ml’s are all relatively (pairwise) prime. • An integer X is mapped into a RNS L-tuple X  (x1, x2, …, xL), where xl = X mod ml , for l = 1, 2, …L. • ForX = (x1, x2, …, xL) and Y = (y1, y2, …, yL), the algebraic operations +, – or * are defined by zl = xl yl mod ml, for l = 1, 2, …L, and the resultis Z = (z1, z2, …, zL). Digital Kommunikationselektronik TNE064 Lecture 1