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Upgrading the STAR TPC FEE (R & D Phase)

Upgrading the STAR TPC FEE (R & D Phase). Fred Bieser. R&D Program Goals. Develop solid technical approach for upgrading TPC (and FTPC) readout speed and data quality Basis for eventual upgrade implementation (in tandem with DAQ) to support >1kHz rate of event presentation to level 3.

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Upgrading the STAR TPC FEE (R & D Phase)

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  1. Upgrading the STAR TPC FEE(R & D Phase) Fred Bieser

  2. R&D Program Goals Develop solid technical approach for upgrading TPC (and FTPC) readout speed and data quality Basis for eventual upgrade implementation (in tandem with DAQ) to support >1kHz rate of event presentation to level 3

  3. History • EOS @ Bevatron (1990) • 15K channels; 100/sec SCA + ext. ADCs • NA49 @ CERN SPS (1995) • 186K channels; 16/sec SCA/ADC • STAR @ RHIC (1998) • 137K channels; 100/sec SCA/ADC + Gigabit links

  4. The Future • ALICE @ LHC (2007) • 570K channels, 200 central events/sec • STAR (after upgrade) • 137K channels, 1000 central events/sec

  5. Bottlenecks, shortcomings • Analog store + digitization (SCA/ADC) • Discontinuous sampling • Off-chamber zero suppression • Spatial ‘noise’ preamp shaper analog sample digitize serialize send to DAQ sub. pedestal suppress 0s

  6. Desired Improvements • Higher Event Rate to Level 3 (>1KHz) • Continuous Waveform Sampling • Digital filtering (better shaping) • Zero suppression before Xmission to DAQ preamp shaper digitize adj. baseline suppress 0s serialize send to DAQ

  7. ALTRO Features • 20MHz/10bit ADC per channel (4mW) • 2 stages of adaptive baseline restoration • Tunable pulse shaping (tail corrections) • Continuous Pipelined Digital Processing/Formatting • Output = 4x faster & 4x wider than inputs

  8. R & D Plan Year 1: • Develop science-driven requirements • Evaluate technical approaches (e.g. ALTRO chip developed for ALICE TPC) • Learn about care and feeding of ALTRO chip • Define topology of FEE on a STAR TPC Sector • Define interface to DAQ (both physical and philosophical)

  9. R & D Plan Year 2: • Design FEE card and Readout Controller • Develop STAR-specific algorithms and parameters used within the ALTRO chip • Construct several prototype FEE cards and interface to DAQ • Perform detailed testing/evaluation of prototypes using spare TPC sector

  10. Costs • Major effort = contributed time (free) (myself + jay + other RNC members) • 50% of one post-doc • Part of a junior engineer in second year • Travel (BNL,CERN) • prototype PCBs • Costs: year 1 $80K year 2 $167K

  11. Summary • The goal of this R&D proposal is to prepare for upgrading the performance of the TPC electronics. • We are doing preliminary work now and are ready to rapidly move ahead once we are approved.

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