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Evaluation of 'OpenCL for FPGA' for DAQ and Acceleration in HEP Applications

This presentation discusses the evaluation of 'OpenCL for FPGA' as a potential solution for data acquisition and acceleration in High Energy Physics (HEP) applications. The focus is on the challenges and benefits of using FPGA and the potential of OpenCL in addressing these challenges. The presentation also includes examples of implementing a FPGA DAQ system and utilizing OpenCL for algorithm acceleration. Conclusions highlight the potential of OpenCL for FPGA and its impact on the future of FPGA utilization.

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Evaluation of 'OpenCL for FPGA' for DAQ and Acceleration in HEP Applications

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  1. Evaluation of 'OpenCL for FPGA' for DAQ and Acceleration in HEP applications CHEP 2015 Srikanth S Marie Curie Fellow: ICE-DIP srikanth.sridharan@cern.ch • 13/04/2015

  2. SrikanthSridharan – ICE-DIP Project

  3. The Grand Challenge for proposed upgrade of LHCb experiment • 500 Data sources each generating data at 100 Gbps • Requires FPGAs for • DAQ modules • Adaptive, high performance • Low Level Trigger decisions • Algorithm acceleration • FPGAs are great • High Performance • Flexibility - Build anything • But… SrikanthSridharan – ICE-DIP Project

  4. FPGA pains • Programmability, Programmability, Programmability • Using Hardware Description Languages (HDLs) • At Register transfer level (RTL) abstraction • Create Custom Memory Hierarchies • Manage Communication with PC • Create PC side SW that plays nice with all this SrikanthSridharan – ICE-DIP Project

  5. OpenCL for FPGA • An unified programming model for accelerating algorithms on heterogeneous systems • C based programming language • System level design (Host CPU+FPGA) • Memory Hierarchy auto generated • Host CPU-FPGA communication abstracted away • Potential to integrate existing VHDL/Verilog IP SrikanthSridharan – ICE-DIP Project

  6. OpenCL for FPGA SrikanthSridharan – ICE-DIP Project

  7. End to end DAQ + Acceleration system with ‘OpenCL for FPGA’ ? • OpenCLspec targets • Algorithm Acceleration • Not FPGA design • But, How about ‘OpenCL for FPGA’ • More than Acceleration? • A DAQ system with OpenCL? • Only one way to find out • Go ahead and implement one SrikanthSridharan – ICE-DIP Project

  8. An existing FPGA DAQ system Source Emulator Header Generator • A DAQ module to packetize streaming data • Attempt to implement the functionality in OpenCL kernels • But was it enough? SrikanthSridharan – ICE-DIP Project

  9. OpenCLAlgorithm Acceleration • Hough Transform • Used for particle track reconstruction in LHCb for the future VertexDetector • Find tracks from the Hit data of the detector • ExisitingOpenCL GPU code ported to FPGA SrikanthSridharan – ICE-DIP Project

  10. Erratum: on this slide a comparison measurement was shown which iserroneous and has been retracted. We will show a corrected measurementin the paper. First Name and Family Name – ICE-DIP Project

  11. Conclusions • FPGAs have always been capable devices • Performance, Versatility, Flexibility • But so have been limited by the usability • Separate and HW oriented programming model • OpenCL is a game changer • Unlocking the potential of FPGAs much easier • Sure, there are some road blocks • But future of OpenCL for FPGA is definitely bright SrikanthSridharan – ICE-DIP Project

  12. Thank You! SrikanthSridharan – ICE-DIP Project

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