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PIDS Key Issues

PIDS Key Issues. Peter M. Zeitzoff ITWG Meeting: Grenoble, France April 26-27, 2001. Memory and logic Memory: DRAM, including DRAM transfer device; nonvolatile memory Transistors: high performance, low (operating) power, low (standby) power Interconnect Mixed signal

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PIDS Key Issues

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  1. PIDS Key Issues Peter M. Zeitzoff ITWG Meeting: Grenoble, France April 26-27, 2001

  2. Memory and logic Memory: DRAM, including DRAM transfer device; nonvolatile memory Transistors: high performance, low (operating) power, low (standby) power Interconnect Mixed signal Reliability: includes ESD, latchup, single event upset Organization of PIDS Technology Requirements Tables

  3. “a” area factor: timing of shift from 8 to 6 Retention time: explain 256 ms64ms Add transfer device requirements Key Issues: DRAM

  4. Especially for low operating power, high K is apparently required in 2003 Low standby power, circuit and architecture techniques can probably push high K beyond 2003 Further analysis required for confirmation Key Issues: Low Power Logic

  5. Transistor performance (CV/I) can continue to scale at historic rates, but: Dynamic and static power dissipation must be dealt with by circuit and system design Higher Ioff and gate leakage Less Vdd and Tox scaling (vs. Lg) High K apparently needed by 2004 New structure (dual gate?) needed by 2007, perhaps earlierpursue this quickly Technology performance improvements (SOI/low T/high mobility/?) needed by around 2007 Further analysis needed for confirmation Key Issues: High Performance Logic

  6. Mixed signal Better comparison between bipolar and CMOS numbers needed Will work to strengthen technology focused requirements Novel devices Will be major section of PIDS chapter New terminology: “emerging research devices” Will include wide variety of devices, from relatively short-range to very long-range Will have extensive linked information in memory Key Issues: Mixed Signal, Novel Devices

  7. DRAM and non-volatile memory: agreeing on values for key technology requirements Key PIDS deliverables to FEP Allowable poly depletion Rsd/Ron specification: joint modeling of Rsd B-B (junction) leakage specification Re-evaluate 10% DLg specification Re-evaluate 4-6 ohms/sq. gate sheet resistance spec. Key Issues with FEP

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