PIDS Scope

1. PIDS Status and Key Issues: 2004 and 2005 ITRSPeter M. Zeitzoff for PIDS Technology Working GroupITRS Open MeetingJuly 14, 2004San Francisco

2. PIDS = Process Integration, Devices, and Structures Main concerns Process integration and full process flows MOSFET and passive devices and structures Device physical and electrical characteristics and requirements Broad issues of device and circuit performance and power dissipation, particularly as they drive overall technology requirements Reliability PIDS Scope

3. Logic: both high performance and low power logic Low power focused on mobile applications Memory: both DRAM and Non-volatile memory Reliability RF and mixed-signal/analog technology for wireless communications Focused toward wireless communication and considerably broadened in 2003 ITRS To be discussed in a separate presentation Emerging Research Devices: focused on devices and technologies for 2009 and beyond New in 2001 ITRS Broadened and a sharper evaluation focus added in 2003 ITRS To be discussed in a separate presentation by Jim Hutchby PIDS Subcategories

4. 2004 PIDS section: only minor updates and corrections from 2003 version Beginning preparation for 2005 PIDS Status

5. Non-volatile memory (NVM) Flash (NOR and NAND), FeRAM, SONOS, and MRAM Flash issues Difficult scaling issues for interpoly dielectric and tunneling dielectric thicknesses Does flash F catch up with or even surpass DRAM half pitch? Possible transfer of phase change and floating body memory from ERD to PIDS in 2005 DRAM 2005: scaling of DRAM half pitch, “a” factor, etc. New survey of key DRAM companies needed What was DRAM half pitch in 2003, and 2004 Memory

6. Reliability requirements on a per chip basis are constant Relative reliability required per transistor becomes more stringent with scaling Relative reliability required per meter of interconnect becomes more stringent with scaling Reliability challenges are associated with new materials and structures: high-k/metal gate stack, copper/low-k, elevated S/D, ultra-thin body fully depleted SOI, multiple-gate, etc. Reliability models, data, and reliability qualification should predate production start Detailed report from RTAB of International SEMATECH on key reliability challenges will be linked Reliability

7. Simple models capture essential MOSFET physics  embedded in a spreadsheet Verified vs. MASTAR (sophisticated device model from STM), literature data, and PIDS member knowledge Initial choice of scaled MOSFET parameters is made Using spreadsheet, MOSFET parameters are iteratively varied to meet ITRS targets This is one optimal scaling scenario 2003 models more comprehensive and accurate than in 2001 ITRS Types of Logic High Performance: target is historical 17%/year transistor performance increase Low Power (especially for mobile applications): target is specific, low level of leakage current Low Standby Power (LSTP): very low power (i.e., cellphone) Low Operating Power (LOP): low power, rel. high performance (i.e., notebook computer, video camcorder Logic: Scaling Approach and Categories

8. t, LOP t, LSTP Isd,leak: HP Isd,leak: LOP t, HP Isd,leak: LSTP 17%/year performance improvement rate NMOSFET Performance and Leakage Scaling

9. Overall 1/t and Isd,leak scaling scenarios for high-performance, LSTP, and LOP Particularly LOP: definition, tradeoff between and fit of LOP between LSTP and high-performance logic Relations between Isd,leak and Jg,limit Jg,limit = (Isd,leak/Lg) x ([Temp Factor]/[Stack & Overlap Factor]) Stack & Overlap Factor = 3—very rough estimate More attention to PMOSFETs Timeline of potential solutions Key PIDS Logic Issues for 2005 ITRS

10. Review modeling Fringe and overlap capacitance Scaling of mobility enhancement Modeling and scaling of enhancements due to advanced devices (single- and multiple-gate) MASTAR modeling will be important here Quasi-ballistic transport With FEP Improved modeling of S/D: Rsd, S/D lateral abruptness, xj, and halo Poly depletion and quantum effects Key PIDS Logic Issues for 2005 ITRS (con’t.)

11. These lnnovations are required to meet scaling performance goals Enhanced mobilitystrained Si High-performance (HP): 2004 (90 nm node) LOP & LSTP: 2008 (57 nm node) High-k gate dielectric LSTP and LOP: 2006 (70 nm node) HP: 2007 (65 nm node) Metal gate electrode: 2007 (65 nm node) for High-Performance, 2008 (57 nm node) for LOP and LSTP Advanced MOSFETs: FDSOI, probably followed by double gate or multi gate 2008 (57 nm node): HP 2012 (35 nm node): LOP & LSTP Enhanced vsat (quasi-ballistic transport) HP: 2012 (35 nm node) LOP: 2015 (25 nm node) LSTP: 2018 (18 nm node) Review Timing of Key Logic Technology Innovations

12. 1.E+02 EOT 20 1.E+01 15 1.E+00 EOT (A) Jg (A/cm2) Jg,sim,SiON 1.E-01 10 1.E-02 Jg,max 5 1.E-03 0 1.E-04 2003 2005 2007 2009 2011 2013 2015 2017 Calendar Year LSTP: EOT and Gate Leakage Current Density (Jg) Scaling 1.E+03 25

13. Timeliness of key innovations, including high-k gate dielectric (LSTP and LOP first), advanced MOSFET structures (FDSOI or multi-gate FETs), etc.many changes in a short time High leakage current for high-performance logicstatic power dissipation issues Meeting drive current (Ion) requirements for scaled technologies: enhanced mobility (strained Si), advanced MOSFET structures, and quasi-ballistic operation likely needed Meeting leakage current requirements for low-power logic with scaling, especially for LSTP Junction leakage becomes an important problem; advanced SOI MOSFET structures help considerably Short channel effects become difficult to control adequately with scaling: advanced MOSFET structures likely needed Summary of Key Logic Issues