PIDS Scope

1. PIDS Status and Key Issues: 2003 ITRSPeter M. Zeitzoff for PIDS Technology Working GroupITRS Open MeetingJuly 16, 2003San Francisco

2. PIDS = Process Integration, Devices, and Structures Main concerns Process integration and full process flows MOSFET and passive devices and structures Device physical and electrical characteristics and requirements Broad issues of device and circuit performance and power dissipation, particularly as they drive overall technology requirements Reliability PIDS Scope

3. Logic: both high performance and low power logic Low power focused on mobile applications Memory: both DRAM and Non-volatile memory RF and mixed-signal/analog technology for wireless communications Focused toward wireless communication and considerably broadened in 2003 ITRS To be discussed in a separate presentation by Bin Zhao Reliability Emerging Research Devices: focused on devices and technologies for 2009 and beyond New in 2001 ITRS Broadened and a sharper evaluation focus added in 2003 ITRS To be discussed in a separate presentation by Jim Hutchby PIDS Subcategories

4. Simple models capture essential MOSFET physics  embedded in a spreadsheet Verified vs. MASTAR (sophisticated device model from STM), literature data, and PIDS member knowledge Initial choice of scaled MOSFET parameters is made Using spreadsheet, MOSFET parameters are iteratively varied to meet ITRS targets This is one optimal scaling scenario 2003 models more comprehensive and accurate than in 2001 ITRS Types of Logic High Performance: target is historical 17%/year transistor performance increase Low Power (especially for mobile applications): target is specific, low level of leakage current Low Standby Power (LSTP): very low power (i.e., cellphone) Low Operating Power (LOP): low power, rel. high performance (i.e., notebook computer, video camcorder) 17%/year transistor performance increase still achieved Logic: Scaling Approach and Categories

5. Significantly improved models High-Performance Logic Somewhat lower Isd,leak and Igate,leak Earlier deployment of enhanced mobility (strained Si) Higher Vdd Low-power Logic Slightly greater Isd,leak and Igate,leak High-k gate dielectric needed first both for LOP and LSTP, but one year later than projected in 2001 LOP: Vdd lower Slightly better transistor performance rate of improvement Logic: Changes from 2001 ITRS

6. High-Performance Logic Technology Requirements Table (DRAFT)

7. NMOSFET Performance and Leakage CV/I, LOP CV/I, LSTP Isd,leak: HP Isd,leak: LOP CV/I, HP Isd,leak: LSTP

8. Enhanced mobilitystrained Si HP: 2004 (90 nm node) LOP & LSTP: 2008 (57 nm node) High-k gate dielectric LSTP and LOP: 2006 (70 nm node) HP: 2007 (65 nm node) Metal gate electrode: 2007 (65 nm node) for High-Performance, 2008 (57 nm node) for LOP and LSTP Advanced MOSFETs: FDSOI, probably followed by double gate or multi gate 2008 (57 nm node): HP 2012 (35 nm node): LOP & LSTP Enhanced vsat (quasi-ballistic transport) HP: 2012 (35 nm node) LOP: 2015 (25 nm node) LSTP: 2018 (18 nm node) Likely Timing of Key Innovations (“Technology Boosters”)

9. 1.E+02 EOT 20 1.E+01 15 1.E+00 EOT (A) Jg (A/cm2) Jg,sim,SiON 1.E-01 10 1.E-02 Jg,max 5 1.E-03 0 1.E-04 2003 2005 2007 2009 2011 2013 2015 2017 Calendar Year LSTP: EOT and Gate Leakage Current Density (Jg) Scaling 1.E+03 25

10. Timeliness of key innovations, including high-k gate dielectric (LSTP and LOP first), advanced MOSFET structures (FDSOI or multi-gate FETs), etc.many changes in a short time High leakage current for high-performance logicstatic power dissipation issues Meeting drive current (Ion) requirements for scaled technologies: enhanced mobility (strained Si), advanced MOSFET structures, and quasi-ballistic operation likely needed Meeting leakage current requirements for low-power logic with scaling, especially for LSTP Junction leakage becomes an important problem; advanced SOI MOSFET structures help considerably Short channel effects become difficult to control adequately with scaling: advanced MOSFET structures likely needed Key Overall Logic Issues

11. Flash: NOR and NAND Flash scaling follows MPU/ASIC half pitch scaling Difficult scaling issues for interpoly dielectric and tunneling dielectric thicknesses FeRAM Technology tables being worked on SONOS New in 2003 PIDS (transferred from 2001 ERD): expected to be in production Initial requirements table being reviewed MRAM New in 2003 PIDS (transferred from 2001 ERD): expected to be in production Requirements table being developed Non-Volatile Memory (NVM)

12. Reliability requirements on a per chip basis are constant Relative reliability required per transistor becomes more stringent with scaling Relative reliability required per m of interconnect becomes more stringent with scaling Reliability challenges are associated with new materials and structures: high-k/metal gate stack, copper/low-k, elevated S/D, ultra-thin body fully depleted SOI, etc. Reliability models, data, and reliability qualification should predate production start Detailed report from RTAB of International SEMATECH on key reliability challenges will be linked Reliability

13. 2004 DRAM half pitch is 90 nm Detailed survey of DRAM companies’ plans was completed in late 2002: these plans are slowed somewhat compared to 2001 ITRS projections Stacked capacitor storage dielectric EOT Cell size “a” factor Bit density and bits per chip Etc. Technology tables have taken survey results into account DRAM

14. DRAM Storage Cell Dielectric Thickness Scaling

15. DRAM Cell area factor “a”

16. DRAM Bit density Scaling

17. PIDS is concerned with process integration, devices, structures, and electrical behavior Logic High-performance logic focused on performance Low power logic focused on low leakage Timeliness of key innovations is important: strained Si, high-k/metal gate, fully depleted SOI all projected by 2009 NVM: SONOS and MRAM added this year Reliability: key challenges are associated with new materials and advanced devices DRAM: survey indicates some slowing of scaling plans, technology requirements tables reflect this Summary