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ECE 545 Introduction to VHDL. Course web page:. ECE web page  Courses  Course web pages  ECE 545. http://ece.gmu.edu/courses/ECE545/index.htm. Kris Gaj. Research and teaching interests: reconfigurable computing computer arithmetic cryptography network security Contact:

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  1. ECE 545 Introduction to VHDL Course web page: ECE web page  Courses  Course web pages  ECE 545 http://ece.gmu.edu/courses/ECE545/index.htm

  2. Kris Gaj • Research and teaching interests: • reconfigurable computing • computer arithmetic • cryptography • network security • Contact: • Science & Technology II, room 223 • kgaj01@yahoo.com, kgaj@gmu.edu • (703) 993-1575 Office hours:Monday, Wednesday 7:30-8:30 PM and by appointment

  3. ECE 545 Part of: MS in Computer Engineering Required course in two concentration areas: Digital Systems Design Microprocessor and Embedded Systems Elective course in the remaining concentration areas MS in Electrical Engineering Elective

  4. Fall 2005 Enrollment as of August 31, 2005 MS in IS 1 PhD in IT 1 PhD in ECE 1 MS in CpE 13 MS in EE 12

  5. Courses Design level Computer Arithmetic VLSI Design Automation VLSI Test Concepts Introduction to VHDL algorithmic ECE 645 ECE 681 ECE 545 register-transfer ECE 682 gate ECE 586 Digital Integrated Circuits transistor ECE 699 MixedSignals VLSI layout Semiconductor Device Fundamentals MOS Device Electronics ECE 584 ECE684 devices

  6. Core courses • There are TWO core courses common for all concentration • areas: • CS 571 Operating Systems – H. Aydin, S. Setia, C. Snow, project, C/C++ or Java • Pros: • Prerequisite for many other courses and projects • HLL (High Level Language) refresher • Offered regularly in Fall and Spring • ECE 548 Sequential Machine Theory – K. Hintz, R. Schneider • Pros: • Common theoretical and mathematical foundation used in all • concentrations • Offered regularly in Spring • Not a strong prerequisite for any other course; can be taken any time • during the curriculum.

  7. DIGITAL SYSTEMS DESIGN • Concentration advisor: Ken Hintz • 1. ECE 545 Introduction to VHDL – K. Gaj, K. Hintz, projects, VHDL, Aldec/Synplicity/Xilinx and ModelSim/Synopsys • 2. ECE 645 Computer Arithmetic: HW and SWImplementation – K. Gaj, projects, VHDL, Aldec/Synplicity/Xilinx and ModelSim/Synopsys • 3. ECE 586 Digital Integrated Circuits – D. Ioannou • 4. ECE 681 VLSI Design Automation – K. Kazi, projectz, VHDL, ModelSim/Synopsys

  8. MICROPROCESSOR AND EMBEDDED SYSTEMS • Concentration advisor: Peter Pachowicz • ECE 511 Microprocessors– R. Barnes, P. Pachowicz, • ECE 545 Introduction to VHDL– K. Gaj, K. Hintz, project, VHDL, Aldec/Synplicity/Xilinx and ModelSim/Synopsys • ECE 611 Advanced Microprocessors– R. Barnes, D. Tabak • ECE 612 Real-Time Embedded Systems– K. Hintz

  9. MICROPROCESSOR AND EMBEDDED SYSTEMS • Concentration advisor: Peter Pachowicz • ECE 511 Microprocessors– P. Pachowicz • ECE 545 Introduction to VHDL– K. Hintz, K. Gaj, project, VHDL, Aldec/ModelSim, Synplicity/Synopsys • ECE 611 Advanced Microprocessors– D. Tabak • ECE 612 Real-Time Embedded Systems– K. Hintz

  10. Concentration Area Advisors DIGITAL SYSTEMS DESIGN:Ken Hintz COMPUTER NETWORKS: Brian Mark NETWORK AND SYSTEM SECURITY:Kris Gaj MICROPROCESSOR AND EMBEDDED SYSTEMS: Peter Pachowicz

  11. ECE 545 Projects Lecture Project 1 25 % Project 2 10 % Project 3 15 % Homework 10 % Midterm exams Midterm 1 20 % in class Midterm 2 20 % take home

  12. Lecture (1) Lecture 1 - Introduction to VHDL for Synthesis Lecture 2 - Data Flow & Structural Modeling of Combinational Logic. Packages and Components. Lecture 3 – Behavioral Modeling of Sequential Logic. Registers, Counters, Shift Registers. Simple Testbenches. Lecture 4 - Introduction to FPGA Devices & Tools Lecture 5 - Finite State Machines Lecture 6 - Algorithmic State Machines Lecture 7 – Advanced Testbenches, File I/O, Memory Lecture 8 - Mixed Style RTL Modeling Lecture 9 - Advanced Examples: Sorting, Average, MAX, MIN Midterm 1

  13. Lecture (2) Lecture 10 - Variables, Functions and Procedures Lecture 11 – ASIC Logic Synthesis with Synopsys Design Compiler Lecture 12 – Advanced Data Types. Operators and Attributes. Lecture 13 - Timing. Event-Driven Simulation Lecture 14 - Behavioral Modeling - The DLX Computer System Midterm Exam 2

  14. Textbooks Required Textbooks: Volnei A. Pedroni, Circuit Design with VHDL, The MIT Press, 2004 Sundar Rajan, Essential VHDL: RTL Synthesis Done Right, S & G Publishing, 1998 Supplementary Textbooks: Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 2nd Edition, McGraw-Hill, 2005 Peter J. Ashenden, The Designer's Guide to VHDL, 2nd Edition, San Francisco:Morgan Kaufman, 1996, 2002

  15. Midterm exam 1 • 2 hours 30 minutes • in class • design-oriented • open-books, open-notes • practice exams will be available on the web Tentative date: Wednesday, October 26th

  16. Midterm Exam 2 • take-home • full design, including logic synthesis and timing analysis with Synopsys Design Compiler • 48 hours Tentative date: Saturday, Sunday, December 10-11

  17. Project technologies FPGA: Field Programmable Gate Arrays and ASIC: semi-custom Application Specific Integrated Circuits

  18. World of Integrated Circuits Integrated Circuits Full-Custom ASICs Semi-Custom ASICs User Programmable PLD FPGA PAL PLA PML LUT (Look-Up Table) MUX Gates

  19. Two competing implementation approaches FPGA FieldProgrammable GateArray ASIC ApplicationSpecific IntegratedCircuit • bought off the shelf • and reconfigured by • designers themselves • designs must be sent • for expensive and time • consuming fabrication • in semiconductor foundry • no physical layout design; • design ends with • a bitstream used • to configure a device • designed all the way • from behavioral description • to physical layout

  20. Which Way to Go? ASICs FPGAs Off-the-shelf High performance Low development cost Low power Short time to market Low cost in high volumes Reconfigurability

  21. I/O Block I/O Block I/O Block I/O Block What is an FPGA Chip ? • Field Programmable Gate Array • A chip that can be configured by user to implement different digital hardware • Configurable Logic Blocks and Programmable Switch Matrices • Bitstream to configure: function of each block & the interconnection between logic blocks Source: [Brown99]

  22. CLB Structure

  23. CLB Slice COUT YB Carry & Control Logic Look-Up Table Y G4 G3 G2 G1 S D Q O CK EC R F5IN BY SR XB Look-Up Table Carry & Control Logic X S F4 F3 F2 F1 D Q O CK EC R CIN CLK CE SLICE

  24. LUT (Look-Up Table) Functionality • Look-Up tables are primary elements for logic implementation • Each LUT can implement any function of 4 inputs

  25. Major FPGA Vendors SRAM-based FPGAs • Xilinx, Inc. • Altera Corp. • Atmel • Lattice Semiconductor Flash & antifuse FPGAs • Actel Corp. • Quick Logic Corp. Share over 60% of the market

  26. Xilinx FPGA Families • Old families • XC3000, XC4000, XC5200 old 0.5µm, 0.35µm and 0.25µm technology. Not recommended for modern designs. • Low-cost families • Spartan/XL – derived from XC4000 • Spartan-II – derived from Virtex • Spartan-IIE – derived from Virtex-E • Spartan-3 • High-performance families • Virtex (0.22µm) • Virtex-E, Virtex-EM (0.18µm) • Virtex-II, Virtex-II PRO (0.13µm) • Virtex-4 (0.09µm)

  27. Design process (1) Specification Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds….. VHDL description (Your VHDL Source Files) Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31downto0); data_output: out std_logic_vector(31downto0); out_full: in std_logic; key_input: in std_logic_vector(31downto0); key_read: out std_logic; ); end AES_core; Functional simulation Synthesis Post-synthesis simulation

  28. Design process (2) Implementation (Mapping, Placing & Routing) Timing simulation Configuration On chip testing

  29. Design Process control from Active-HDL

  30. Simulation Tools Many others…

  31. Logic Synthesis VHDL description Circuit netlist architecture MLU_DATAFLOW of MLU is signal A1:STD_LOGIC; signal B1:STD_LOGIC; signal Y1:STD_LOGIC; signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC; begin A1<=A when (NEG_A='0') else not A; B1<=B when (NEG_B='0') else not B; Y<=Y1 when (NEG_Y='0') else not Y1; MUX_0<=A1 and B1; MUX_1<=A1 or B1; MUX_2<=A1 xor B1; MUX_3<=A1 xnor B1; with (L1 & L0) select Y1<=MUX_0 when "00", MUX_1 when "01", MUX_2 when "10", MUX_3 when others; end MLU_DATAFLOW;

  32. Synthesis Tools … and others

  33. Features of synthesis tools • Interpret RTL code • Produce synthesized circuit netlist in a standard EDIF format • Give preliminary performance estimates • Some can display circuit schematics corresponding to EDIF netlist

  34. Implementation • After synthesis the entireimplementation process is performed by FPGA vendor tools

  35. Mapping LUT0 LUT4 LUT1 FF1 LUT5 LUT2 FF2 LUT3

  36. Placing FPGA CLB SLICES

  37. Routing FPGA Programmable Connections

  38. Design Process control from Active-HDL

  39. Top Level ASIC Digital Design Flow Design Inception RTL Design Synthesis Macro Development Place + Route Physical Verification Design Complete

  40. RTL Design Design Function Digital Tool Design Inception Design Inception Cadence NC Verilog RTL Design Mentor Graphis ModelSim Lint Checking Cadence Hal ( users discression) FPGA Verification Xilinx ISE ( users discression) Code Coverage Cadence ICT ( users discression) Cadence NC Verilog Testbench Developement Mentor Graphics ModelSim Mixed Mode Simulation Cadence AMS Designer Formal Verification Cadence Conformal Agilent ADS System Interface Simulation Matlab Synthesis Synthesis + Macro Synthesis + Macro Development Development

  41. Synthesis + Macro Development Design Function Digital Tool RTL RTL Synopsys DC Synthesis Macro Generation Artisan Cadence RC Synopsys DFT Compiler DFT Macro Verification Mentor Graphics Calibre Cadence RC Artisan / Macro Rules Generation / Synopsys PrimeTime Static Timing Analysis Library Generation Cadence DFII Cadence Conformal Logical Equivalency Verification Verification Cadence NC Verilog Gate - Level Simulation Mentor Graphics Modelsim Place + Route Place + Route

  42. Place + Route Digital Tool Design Function Synthesis Synthesis Floorplan Macro Placement / Std Cell Placement Cadence Encounter Placement - Based Optimization Clock Tree Synthesis Static Synopsys Timing Prime - Analysis Time Route Cadence NanoRoute Spare Cells / Decoupling Mentor Graphics ATPG Cap Filler Cells Cadence Encounter FastScan RC Extraction Cadence Fire & Ice QX Signal Integrity Cadence CeltIC / Voltage Storm Metal Fill Cadence Encounter Verification Verification

  43. Physical Verification Digital Tool Design Function Placed + Routed Placed + Routed Design Design GDSII Preparation / Simulation Preparation Cadence DFII Cadence DFII Schematic Preparation Back Annotated Simulation Layout Chip Finishing Cadence Virtuoso Cadence NC Verilog DRC LVS Mentor Graphics Calibre ERC Synopsys Nanosim Top - Level Simulation Cadence AMS Designer Design Complete Design Complete

  44. CAD software available at GMU (1) VHDL simulators • Aldec Active-HDL (under Windows) • available in the FPGA Lab, S&T II, room 203 • student edition can be purchased on an individual • basis ($59.95 + S&H) • ModelSim (under Unix) • available from all PCs in the ECE educational labs • using an X-terminal emulator • available remotely from home using a fast Internet • connection

  45. CAD software available at GMU (2) Tools used for logic synthesis FPGA synthesis • Synplicity Synplify Pro (under Windows) • Xilinx XST(under Windows) • available in the FPGA Lab, S&T II, room 203 ASIC synthesis • Synopsys Design Compiler (under Unix) • available from all PCs in the ECE educational labs • using an X-terminal emulator • available remotely from home using a fast Internet • connection

  46. CAD software available at GMU (3) Tools used for implementation (mapping, placing & routing) in the FPGA technology • Xilinx ISE (under Windows) • available in the FPGA Lab, S&T II, room 203

  47. Projects – Overview Project 1 (25 points) mid-September – October (~6 weeks) Application:cryptography OR digital signal processing Technology:FPGA Target:synthesizable code, timing, resource usage Project 2 (10 points) November (~3 weeks) Application: the same as in Project 1 Technology:ASIC Target:revised synthesizable code, synthesis scripts, timing, resource usage, comparison Project 3 (15 points) December (~3 weeks) Application: simple microprocessor/microcontroller Target: behavioral code

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