ECE 667 Spring 2011 Synthesis and Verification of Digital Systems

Oct 16, 2012

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ECE 667 Spring 2011 Synthesis and Verification of Digital Systems

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ECE 667 Spring 2011 Synthesis and Verification of Digital Systems

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ECE 667 Spring 2011 Synthesis and Verification of Digital Systems

ECE 667 - Synthesis

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ECE 667 Spring 2011 Synthesis and Verification of Digital Circuits

ECE 667 Spring 2011 Synthesis and Verification of Digital Circuits. Introduction to Logic Synthesis. HDL specification. Front-end parsing. Techn-independent optimization. Technology mapping. Cell library. Manufacturing. Synthesis Flow . Logic synthesis . Specification. a. b.

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ECE 667 Spring 2011 Synthesis and Verification of Digital Systems

ECE 667 Spring 2011 Synthesis and Verification of Digital Systems. Verification Introduction. Outline. Motivation: what is verification, why we need it Verification methods Formal methods Simulation-based functional verification Deterministic test generation.  ?. model. Design 1.

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ECE 667 Spring 2013 Synthesis and Verification of Digital Systems. Multi-level Logic Minimization Factored Forms. Slides adapted (with permission) from A. Kuehlmann, UC Berkeley 2003. Outline. Factored forms Motivation: multi-level logic representation Definitions, theory, examples

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Word-level (decision) Diagrams BMDs, TEDs. ECE 667 Spring 2013 Synthesis and Verification of Digital Systems. Outline. Review of design representations common representations of Boolean and arithmetic functions Motivation for word-level diagrams

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ECE 667 Spring 2013 Synthesis and Verification of Digital Systems

ECE 667 Spring 2013 Synthesis and Verification of Digital Systems. Multi-level Minimization (Kernel-based). Slides adapted (with permission) from A. Kuehlmann, UC Berkeley, 2003. Multi-level Logic Transformation. Basic Operations on multi-level network: 1. Decomposition (single function)

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ABC Logic Synthesis basics ECE 667 Synthesis and Verification of Digital Systems Spring 2011

ABC Logic Synthesis basics ECE 667 Synthesis and Verification of Digital Systems Spring 2011. Archana Rengaraj. Overview. Introduction Previous synthesis methods ABC synthesis And-Inverter Graphs (AIG) representation AIG canonicity and redundancy AIG construction NPN equivalence

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ECE 667 Spring 2011 Synthesis and Verification of Digital Systems

ECE 667 Spring 2011 Synthesis and Verification of Digital Systems. FSM Traversal. O. X. (s,x). (s,x). s. s’. R. Finite State Machine (FSM) Model. FSM M(X,S, , ,O) Inputs: X Outputs: O States: S Next state function, (s,x) : S  X  S

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ECE 667 Spring 2013 Synthesis and Verification of Digital Systems

ECE 667 Spring 2013 Synthesis and Verification of Digital Systems. ABC System Combinational Logic Synthesis. Slides adapted from Alan Mishchenko, UC Berkeley 2010+. Outline. ABC System And-Inverter Graph (AIG) AIG construction AIG optimization Rewriting Substitution Redundancy removal

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ECE 667 Spring 2013 Synthesis and Verification of Digital Systems

ECE 667 Spring 2013 Synthesis and Verification of Digital Systems. Binary Decision Diagrams (BDD). Outline. Background Canonical representations BDD’s Reduction rules Construction of BDD’s Logic manipulation of BDD’s Application to verification and SAT Reading:

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ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Systems

ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Systems. Multi-level Minimization - Algebraic division. Slides adopted (with permission) from A. Kuehlmann, UC Berkeley, 2003. Outline. Division and factorization Definition Examples Algebraic vs Boolean division Algorithms

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ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Systems

ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Systems. Multi-level Minimization Factored forms. Slides adopted (with permission) from A. Kuehlmann, UC Berkeley 2003. Outline. Factored forms Definitions Examples Manipulation of Boolean networks

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ECE 667 Spring 2013 Synthesis and Verification of Digital Systems

ECE 667 Spring 2013 Synthesis and Verification of Digital Systems. Retiming. Retiming. Outline: Problem sequential synthesis Formulation Retiming algorithm. Optimizing Sequential Circuits by Retiming Gate-level Netlist. Netlist of gates and registers: Various Goals:

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ECE 667 Spring 2013 Synthesis and Verification of Digital Systems

ECE 667 Spring 2013 Synthesis and Verification of Digital Systems. Technology Mapping for ASIC (standard cells). Slides adapted (with permission) from A. Kuehlmann, UC Berkeley 2003. Initial logic network. techn-independent optimization. technology mapping. Cell library. manufacturing.

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ECE 667 Spring 2013 Synthesis and Verification of Digital Systems

ECE 667 Spring 2013 Synthesis and Verification of Digital Systems. Boolean Functions SOP Representation. Slides adopted (with permission) from A. Kuehlmann, UC Berkeley 2003. Two-level logic (PLA). Multi-level logic (standard cells). Heuristic (espresso). Exact (QM). Boolean.

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ECE 667 Spring 2013 Synthesis and Verification of Digital Systems

ECE 667 Spring 2013 Synthesis and Verification of Digital Systems. Technology Mapping for FPGAs. D.Chen, J.Cong, DAOMap : A Depth optimal Area Optimization mapping algorithm for FPGA Designs, ICCAD 2004. Programming bit P. F = x 1 ’x 2 ’ + x 1 x 2. 2-Input LUT. x1 x2 F

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ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Systems. Verification Combinational Equivalence Checking. Out. In. CL. PI. Po. CL. Ps. Ns. R. Equivalence Checking. Two circuits are functionally equivalent if they exhibit the same behavior Combinational circuits

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ECE 667 Synthesis and Verification of Digital Systems

ECE 667 Synthesis and Verification of Digital Systems. Exact Two-level Minimization Quine-McCluskey Procedure. Slides adopted (with permission) from A. Kuehlmann, UC Berkeley, 2003. Outline. QM Theorem Generating all primes Single output functions Multiple output functions

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ECE 667 Synthesis and Verification of Digital Systems

ECE 667 Synthesis and Verification of Digital Systems. Multi-level Minimization Algebraic Division. Slides adapted (with permission) from A. Kuehlmann, UC Berkeley, 2003. Outline. Division and factorization Definition Examples Algebraic vs Boolean division Algorithms Applications

383 views • 35 slides

ECE 667 Synthesis and Verification of Digital Systems

Formal Verification Combinational Equivalence Checking. ECE 667 Synthesis and Verification of Digital Systems. Out. In. CL. PI. Po. CL. Ps. Ns. R. Equivalence Checking. Two circuits are functionally equivalent if they exhibit the same behavior Combinational circuits

204 views • 18 slides

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