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Delayed Branch

Delayed Branch. All problems solved? NO, what will happen if...... b loop add $4 $6 $1 .. . loop sub. Add. B loop. Zero ext. =. =. Branch logic. 0. A. ALU. 4. B. +. =. =. 31. +. Sgn/Ze extend. sub. Add. B loop. Zero ext. =. =. Branch logic. 0. A. ALU. 4.

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Delayed Branch

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  1. Delayed Branch • All problems solved? NO, what will happen if...... b loop add $4 $6 $1 .. . loop sub

  2. Add B loop Zeroext. = = Branch logic 0 A ALU 4 B + = = 31 + Sgn/Ze extend

  3. sub Add B loop Zeroext. = = Branch logic 0 A ALU 4 B + = = 31 + Sgn/Ze extend

  4. Delayed Branch - Throughput might decrease, (nop). - Assembler/Compiler dependent. + Keep critical path short

  5. All problems solved now? NO, what will happen if...... .. bal loop add $4 $6 $1 xor .... loop: sub ... .. j $ra

  6. bal loop Zeroext. = = Branch logic ADDR 0x00400004 0 A ALU 4 B + = = 31 + Sgn/Ze extend > ADDR 0x00400000 bal loop

  7. bal loop add Zeroext. = = Branch logic 0 A ALU 4 B + = = 31 + Sgn/Ze extend ADDR 0x00400004 ADDR 0x00400000 bal loop > ADDR 0x00400004 add

  8. bal loop sub add Zeroext. = = Branch logic ADDR 0x00400004 0 A ADDR 0x00400004 ALU 4 B + = = 31 + Sgn/Ze extend • ADDR 0x00400000 bal loop ADDR 0x00400004 add >loop: sub

  9. jr $ra ADDR 0x00400004 Zeroext. = = Branch logic 0 A ALU 4 B + = = 31 + Sgn/Ze extend sub .. .. j $ra

  10. Zeroext. = = Branch logic 0 A ALU 4 B + = = 31 + Sgn/Ze extend Oooh not again!!! 0x00400004 add

  11. Continue at 0x00400008 bal loop sub add Zeroext. = = Branch logic ADDR 0x00400004 4 A ADDR 0x00400008 ALU 4 B + = = 31 + Sgn/Ze extend

  12. jr $ra ADDR 0x00400008 Zeroext. = = Branch logic 0 A ALU 4 B + = = 31 + Sgn/Ze extend sub .. .. j $ra

  13. All Hazards Fixed but: • One “delayed branch” slot

  14. What about “delayed Branch” • Can we avoid it? • How?

  15. Delayed Branch Reg IM DM Reg Branch Logic Direct Branch Branch Logic Reg IM DM Reg

  16. Delayed Branch Zeroext. = = Branch logic 0 A ALU 4 B + = = 31 + Sgn/Ze extend

  17. Direct Branch Zeroext. = = Branch logic Branch logic 0 A ALU 4 B + = = 31 + Sgn/Ze extend

  18. What about the instruction set? • beq $t0 $t0 label? • jr $ra? • NO, DE is not in path! • b label? • OK, but the new branch logic needs an ALU to compute the address

  19. Different branch logic? • Can both branch types coexist? • Yes, no problem, but: • Old type still uses “delay slot”

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