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Unit-1: Instruction Set Category Based on Number of Operand Addressess. Prof.M.Rajasekhara Babu School of Computing Science and Engineering mrajasekharababu@vit.ac.in. OutLine. Recap Session Objectives & Teaching Learning Material Session Plan Introduction
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Unit-1: Instruction Set Category Based on Number of Operand Addressess Prof.M.RajasekharaBabu School of Computing Science and Engineering mrajasekharababu@vit.ac.in
OutLine Recap SessionObjectives & Teaching Learning Material Session Plan Introduction 4-,3-,2-,1-,0- Address Machine instructions Instruction formats Performance Parameters Comparisons on Performance parameters Assignment References
Re-Cap 1. List three categories of instructions based on operation 2. Source and result operand can be in one of three areas ……….. 3. Specify the design issues of Instruction Sets 4. List the elements of instructions
Re-CapMatch the following i. Arithmetic A. Data Processing 1.LOAD, STORE, MOV ii. Logic 2. JNZ, JZ, JNP,JNN i. Memory 3. Add, Sub, MUL B. Data Movement ii. I/O 4. Jump, Goto, break, exit 5. AND, OR, NOT iii. Conditional C. Control 6. IN(), OUT() iv. Un conditional
Objectives & Teaching Learning Material • Session Objectives • To teach the instruction set category based on number of operand address by using instruction formats, how to calculate memory to store, memory to encode, M/As to fetch & Execute an instruction and Memory traffic that enable the students to analyze the program in the above said parameters and make the decision on appropriateness of the program. • Teaching Learning Material • LCD, White board Marker, Presentation slides
4-,3-,2-,1-,and 0- address instructions • Instruction Set categorized into four categories based on number of operand address in the instruction. • 4- Address Instruction • 3-Address Instruction • 2-Address Instruction • 1-Address Instruction • 0-Address Instruction
Memory 4- Address Instruction 8 24 24 24 24 24 Bits / 3 Bytes Op Code ResAddr Op1Addr Op2Addr NextiAddr Op1Addr Op2Addr Op Code ResAddr NextiAddr CPU Example: add M1,M2,M3, nexti M(1)M(2)+M(3) Op1 Op2 + Memory Required to store an Instruction: 5 x 3 bytes = 15 Bytes Resop Memory Required to Encode an Instruction: 1Byte+ 4 x 3 bytes = 13 Bytes Calculation of Memory Accesses To Execute an Instruction To fetch Instruction itself Opcode=1 Op1=1 Op1Addr=1 Op2=1 Op2Addr=1 Res=1 ResAddr=1 Total=3 NextiAddr=1 Total=5 Total Memory Traffic= No. of M/A to fetch + No. of M/A to Execute Total Memory Traffic= 5 + 3 =8
Memory 3- Address Instruction 8 24 24 24 24 Bits / 3 Bytes Op Code ResAddr Op1Addr Op2Addr Op1Addr Op2Addr Op Code ResAddr CPU Example: add M1,M2,M3 M(1)M(2)+M(3) Op1 Op2 + Memory Required to store an Instruction: 4 x 3 bytes = 12 Bytes Resop Memory Required to Encode an Instruction: 1Byte+ 3 x 3 bytes = 10 Bytes PC 24 Calculation of Memory Accesses To Execute an Instruction To fetch Instruction itself Opcode=1 Op1=1 Op1Addr=1 Op2=1 Op2Addr=1 Res=1 ResAddr=1 Total=3 Total=4 Total Memory Traffic= No. of M/A to fetch + No. of M/A to Execute Total Memory Traffic= 4+ 3 =7
Memory 2- Address Instruction 8 24 24 24 24 Bits / 3 Bytes Op Code Op1Addr Op2Addr Op1Addr Op2Addr Op Code CPU Example: add M2,M3 M(2)M(2)+M(3) Op1 Op2 + Memory Required to store an Instruction: 3 x 3 bytes = 09 Bytes Resop Memory Required to Encode an Instruction: 1Byte+ 2 x 3 bytes = 7 Bytes PC 24 Calculation of Memory Accesses To Execute an Instruction To fetch Instruction itself Opcode=1 Op1=1 Op1Addr=1 Op2=1 Op2Addr=1 Res=1 Total=3 Total=3 Total Memory Traffic= No. of M/A to fetch + No. of M/A to Execute Total Memory Traffic= 3+ 3 =6
Memory 1- Address Instruction 8 24 24 24 Bits / 3 Bytes Op Code Op1Addr Op1Addr Op Code CPU Op1 Example: add M2 Op2 + Memory Required to store an Instruction: 2 x 3 bytes = 06 Bytes Resop Acc Memory Required to Encode an Instruction: 1Byte+ 1 x 3 bytes = 4Bytes PC 24 Calculation of Memory Accesses To Execute an Instruction To fetch Instruction itself Opcode=1 Op1=1 Op1Addr=1 Total=1 Total=2 Total Memory Traffic= No. of M/A to fetch + No. of M/A to Execute Total Memory Traffic= 2+ 1 =3
Summary • Instruction Set Category Based on Number of Operands • 4- Address Instruction • 3-Address Instruction • 2-Address Instruction • 1-Address Instruction • 0-Address Instruction • Instruction Format • Memory to store, Memory to encode, M/As to fetch, M/As to Execute and Total memory Traffic
Assignmet • Develop an comparative table for the performance parameters such as memory to store, memory to encode, M/As to fetch , M/As to execute and total memory Traffic for 4-,3-,2-,1-,0- address machine instructions. Consider the following specifications: • Memory word size is 1 byte, Memory/register Address size is 2byte, Opcode size is 1 byte.
References Reference Book Vincent .P. Heuring, Harry F. Jordan “ Computer System design and Architecture” Pearson, 2nd Edition, 2003