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Basic Adders and Counters

ECE 645: Lecture 3. Basic Adders and Counters. Required Reading. Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design. Chapter 5 , Basic Addition and Counting , Sections 5.1-5.5 , pp. 75-85. Half-adder. c. x. HA. s. y. x. y. c. s. 0 0 1 1. 0 1 1 0. 0

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Basic Adders and Counters

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  1. ECE 645: Lecture 3 Basic Adders and Counters

  2. Required Reading Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design Chapter 5, Basic Addition and Counting, Sections 5.1-5.5, pp. 75-85.

  3. Half-adder c x HA s y x y c s 0 0 1 1 0 1 1 0 0 1 0 1 0 0 0 1 2 1 x + y = ( c s )2

  4. Half-adder Alternative implementations (1) a) c = xy s = x  y b) c = x + y s = xy + xy

  5. Half-adder Alternative implementations (2) c) c = xy s = xc + yc = xc  yc

  6. Full-adder x cout FA y s cin cout s cin x y 0 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 2 1 x + y + cin = ( cout s )2

  7. c c s Full-adder Alternative implementations (1) a) s = (x  y)  cin cout = xy + cin (x  y)

  8. Full-adder Alternative implementations (2) b) s = x  y  cin = xycin + xycin + xycin + xycin cout = xy + xcin + ycin

  9. Full-adder Alternative implementations (3) c) x y cout s cin 0 0 1 1 0 1 0 1 0 1 cin cin cin cin cin

  10. x y cout Cout 0 0 1 1 0 1 0 1 y y cin cin S x p A2 D y XOR A1 g Cin 0 1 Full-adder Alternative implementations (4) Implementation used to generate fast carry logic in Xilinx FPGAs p = x  y g = y s= p  cin = x  y  cin

  11. Latency of a k-bit ripple-carry adder Tripple-add = TFA(x,ycout) + + (k-2)  TFA(cincout) + + TFA(cin s) Latency  k  TFA Latency  k

  12. Overflow for signed numbers (1) Indication of overflow Negative + Negative = Positive Positive + Positive = Negative Formulas Overflow2’s complement = xk-1 yk-1 sk-1 + xk-1 yk-1 sk-1 = = ck ck-1

  13. Overflow for signed numbers (2) xk-1 yk-1 ck-1 ck sk-1 overflow ckck-1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 0 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1 0 1 0 0 0 0 1 0

  14. yi xi Bit-serial adder c0 ci+1 start clk si

  15. yi xi d d Digit-serialadder c0 ci+1 start clk d si

  16. Addition of a constant (1) xk-1 xk-2 . . . x1 x0 yk-1 yk-2 . . . y1 y0 variable + constant sk-1 sk-2 . . . s1 s0 variable xk-1 xk-2 . . . xh+1 xh xh-1 . . . x0 yk-1 yk-2 . . . yh+1 1 0 . . . 0 constant + xh xh-1 . . . x0 sk-1 sk-2 . . . sh+1

  17. Addition of a constant (2) . . . xh-1 xh+1 xh x0 xk-1 xh+2 xk-2 . . . ck . . . . . HA/ MHA HA/ MHA HA/ MHA HA/ MHA . . . sk-1 sk-2 . . . xh-1 sh+1 xh x0 sh+2 If yi = 0 Half-adder (HA) yi = 1 Modified half-adder (MHA)

  18. Modified half-adder c x MHA s y x y c s 0 0 1 1 1 0 0 1 0 1 0 1 0 1 1 1 2 1 x + y + 1 = ( c s )2

  19. Incrementer x1 x0 xk-1 x2 xk-2 . . . ck . . HA HA HA HA sk-1 sk-2 . . . s1 s2 x0 Decrementer x1 x0 xk-1 x2 xk-2 . . . ck . . MHA MHA MHA MHA sk-1 sk-2 . . . s1 s2 x0

  20. Possible solutions to the carry propagate problem 1. Detect the end of propagation rather than wait for the worst-case time • 2. Speed-up propagation via • look-ahead • carry skip • carry select, etc 3. Limit carry propagation to within a small number of bits 4. Eliminate carry propagation through the redundant number representation

  21. Analysis of carry propagation Probability of carry generation = (xiyi = 11) Probability of carry propagation = (xiyi = 01 or 10) Probability of carry anihilation = (xiyi = 00 or 11) j j-1 . . . . . . . i+1 i 1 0 … 1 …0 … 1 1 1 1 … 0 …1 … 0 1 11 or 00 01 or 10 Probability of carry propagating from position i to position j  = = probability of propagation probability of anihilation

  22. Expected length of the carry chain that starts at position i (1) Expected length(i, k) = Length of the carry chain Probability of the given length Distance till the end of adder Probability of propagation till the end of adder

  23. Expected length of the carry chain that starts at position i (2) Expected length(i, k) = For i << k Expected length of the carry propagation is  2

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