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An NP-Based Router for the Open Network Lab Memory Map

An NP-Based Router for the Open Network Lab Memory Map. John DeHart. ONL NP Router. Large SRAM Ring. xScale. Assoc. Data ZBT-SRAM. xScale (3 Rings?). Small SRAM Ring. Scratch Ring. SRAM. TCAM. SRAM. ARP. Except. Need ARP. NN Ring. NN. 64KW. Parse, Lookup, Copy (3 MEs).

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An NP-Based Router for the Open Network Lab Memory Map

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  1. An NP-Based Router for the Open Network LabMemory Map John DeHart

  2. ONL NP Router Large SRAM Ring xScale Assoc. Data ZBT-SRAM xScale (3 Rings?) Small SRAM Ring Scratch Ring SRAM TCAM SRAM ARP Except Need ARP NN Ring NN 64KW Parse, Lookup, Copy (3 MEs) Rx (2 ME) Mux (1 ME) QM (1 ME) HdrFmt (1 ME) Tx (1 ME) NN Mostly Unchanged xScale 64KW 64KW 64KW 64KW 64KW 64KW Plugin System Update Requests (Q Thresh. Filters, Etc) 512W 512W 512W 512W 512W New Plugin Ctrl Msgs NN NN NN NN Plugin3 Plugin4 Plugin0 Plugin1 Plugin2 SRAM Needs A Lot Of Mod. 512W 512W Rx Mux HF Copy Plugins Tx Needs Some Mod. Tx, QM Parse Plugin XScale Stats (1 ME) FreeList Mgr (1 ME) SRAM

  3. SRAM Usage • What will be using SRAM? • Buffer descriptors • Current MR supports 229,376 buffers • 32 Bytes per SRAM buffer descriptor • 7 MBytes • Queue Descriptors • Current MR supports 65536 queues • 16 Bytes per Queue Descriptor • 1 MByte • Queue Parameters • 16 Bytes per Queue Params (actually only 12 used in SRAM) • 1 MByte • QM Scheduling structure: • Current MR supports 13109 batch buffers per QM ME • 44 Bytes per batch buffer • 576796 Bytes • QM Port Rates • 4 Bytes per port • Plugin “scratch” memory • How much per plugin? • Large inter-block rings • Rx  Mux •  Plugins •  Plugins • Stats/Counters • Currently 64K sets, 16 bytes per set: 1 MByte • Lookup Results

  4. SRAM Bank Allocation • SRAM Banks: • Bank0: • 4 MB total, 2MB per NPU • Same interface/bus as TCAM • Bank1-3 • 8 MB each • Criteria for how SRAM banks should be allocated? • Size: • SRAM Bandwidth: • How many SRAM accesses per packet are needed for the various SRAM uses? • QM needs buffer desc and queue desc in same bank

  5. Proposed SRAM Bank Allocation • SRAM Bank 0: • TCAM • Lookup Results • SRAM Bank 1 (2.5MB/8MB): • QM Queue Params (1MB) • QM Scheduling Struct (0.5 MB) • QM Port Rates (20B) • Large Inter-Block Rings (1MB) • SRAM Rings are of sizes (in Words): 0.5K, 1K, 2K, 4K, 8K, 16K, 32K, 64K • Rx  Mux (2 Words per pkt): 64KW (32K pkts): 128KB • XScale  Mux (3 Words per pkt): 64KW (21K pkts): 128KB •  Plugin (3 Words per pkt): 64KW each (21K Pkts each): 640KB •  Plugin (3 Words per pkt): 64KW (21K Pkts): 256KB • SRAM Bank 2 (8MB/8MB): • Buffer Descriptors (7MB) • Queue Descriptors (1MB) • SRAM Bank 3 (6MB/8MB): • Stats Counters (1MB) • Global Registers (256 * 4B) • Plugin “scratch” memory (5MB, 1MB per plugin)

  6. SRAM Channel 3 0x000000 0x000000 Reserved for Compiler Variables for Rtr Blocks 0x00FFFF 0x010000 Copy Control Block 0x0101FF 0x100000 Plugin 0 0x010200 HF Init Block 0x010300 Unallocated 0x0FFDFF 0x200000 Plugin 1 0x0FFE00 RX Pkt Counters (Turned off for Perf) 0x0FFE9F 0x300000 Plugin 2 0x0FFEA0 Tx Pkt Counters (turned off for Perf.) 0x0FFF3F 0x400000 Plugin 3 0x0FFF40 Unallocated 0x0FFFFF 0x700000 0x500000 Plugin 4 64 Global Counters 0x7001FF 0x700200 Unallocated 0x700FFF Stats 0x600000 0x701000 Plugin Ctrl Rings (6 Rings, 512W each) 0x703FFF 0x704000 Unallocated 0x700000 0x7FFFFF 0x706000 Reserved for Compiler Variables for Plugins 0x7FFFFF

  7. SRAM Channel 2 0x000000 Buffer Descriptors (0x38000 * 32B) (229376 * 32B) (7MB) 0x100000 0x200000 0x300000 0x400000 0x500000 0x600000 Queue Desc Array (65536 * 16B = 1MB) 0x700000

  8. SRAM Channel 1 0x000000 Q Params (65536 * 16B) 0x600000 RX to Mux SRAM Ring 65536 * 4B 0x100000 QM1 Sched (13109 * 44B= 0x8CD1C) 0x640000 PLC to PL0 SRAM Ring 0x18CD1C QM2 Sched (13109 * 44B= 0x8CD1C) 0x680000 PLC to PL1 SRAM Ring 0x219A38 • QM1 Freelist • (13109 * 4B = 0xCCD4) 0x6C0000 PLC to PL2 SRAM Ring 0x22670C • QM2 Freelist • (13109 * 4B = 0xCCD4) 0x700000 PLC to PL3 SRAM Ring 0x2333E0 QM1 & QM2 Port Rates (10 * 4B) 0x740000 PLC to PL4 SRAM Ring Unallocated 0x780000 0x233418 PLs to Mux SRAM Ring 0x600000 SRAM Rings 0x7C0000 XScale to Mux SRAM Ring 0x7FFFFF 0x7FFFFF

  9. SRAM Channel 0 (2MB) 0x000000 RL DB Results (RL_DB_NUM * 12B) PF DB Results (PF_DB_NUM * 12B) AF DB Results (AF_DB_NUM * 12B) 0x1FFFFF

  10. Scratch (16KB) 0x0000 0x0000 TX Avail TBUF (4B) 0x0400 TO_XSCALE_LD_RING 0x0004 UNALLOCATED 0x0800 TO_XSCALE_EXC_RING 0x007F 0x0080 0x0C00 Mux Memory TO_XSCALE_ERR_RING 0x008F 0x1000 COUNTER_RING 0x0090 UNALLOCATED 0x00FF 0x1400 FREELIST_RING 0x0100 SRAM Ring Occupancy Counters 0x01FF 0x1800 MUX_TO_PLC_RING 0x0200 Per ME Drop Counters 0x02FF 0x1C00 PLC_TO_QM_RING 0x0300 UNALLOCATED 0x03FF 0x2000 QM_TO_HF_RING (temporary) 0x2400 HF_TO_TX_RING 0x2800 UNALLOCATED 0x3FFF

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