Bus Serialization for Reducing Power Consumption

1. Bus Serialization for Reducing Power Consumption Naoya Hatta†, Niko Demus Barli††,Chitaka Iwama†, Luong Dinh Hung†,Daisuke Tashiro†, Shuichi Sakai†, Hidehiko Tanaka††† † University of Tokyo †† Texas Instruments Japan ††† Institute of Information Security

2. Introduction • Wiring power consumption is an important issue on VLSI design • SoC and Chip Multiprocessor require buses with long wires • Bus serialization for reducing bus power consumption

3. Outline • Proposition • Objective • Bus Serialization • Layout Optimization • Evaluations • Conclusion • Future Works

4. Proposition

5. Throughput must not decrease We want to reduce Power Objective T = M f • T: Throughput • M: The number of wires • f: Bus frequency P = a T C V2 • P: Power • a: Activity • C: Bus capacitance • V: Voltage swing

6. Latch Serializer Deserializer Latch Wire Wire Conventional Bus Serialized Bus Bus Serialization • Reduce bus capacitance • - by decreasing • the number of wires Low power and high frequency

7. Layout Changes Pitch Pitch • The number of wires (M) decreases • Wire resistance (R) decreases • Wire capacitance (C) decreases Without increasing area

8. M decreases Require higher f - for remaining T T = M f Meet the requirement • R, C decrease f increases f ∝ 1 / R C Objective • C decreases Power decreases P = a T C V2 Parameters Change ?

9. T > 100 % Minimum C (=Minimum P) Best width Layout Optimization

10. P = f C V2 C  C / 2 Power doesn’t decrease? f  2 f P = M f C V2 M  M / 2 Power decreases! C  C / 2 f  2 f Why power decreases?

11. Evaluation

12. Condition • Bus Specification • Bus width: 64bit • The number of wires (conventional): 64 • The number of wires (serialized): 32 • Wire Configurations (width, height, etc…) • From International Technology Roadmap for Semiconductor 2002 • Bit pattern • Address bus and data bus between L1 cache and L2 cache • L1 cache (data/inst) :16KB, 2way, 64byte block • SPECint95 benchmark • Compare to conventional (fully parallel) bus

13. Bus Capacitance The effect of serialization increases as gate length shrinks

14. Bus Power Consumption Power decreases by 34%

15. 1 1 0 0 0 0 0 1 Extra Transition Power is consumed 1 0 1 0 0 0 0 1 Why Power Increases? Conventional Bus • The number of transitions increases by serialization • When the same bit pattern is transferred every cycle, extra transition occurs. • In address bus, this situation frequently appears. Serialized Bus

16. 0010011010 0010011011 0010011100 0010011010 0010011011 0010011100 0010011010 0000000001 0000000111 Extra Transition doesn’t occur Extra Transition occurs Differential Data Transfer (DDT) Bit Pattern Normal DDT • Transfer the difference between present data and previous data

17. Bus Power Consumption (DDT) Power decreases by 27%

18. Comparison • DDT is useful in Address. • In Data, not useful • In 45 nm technology, power decreases by about 30%

19. Power of Peripheral Circuits The additional power of peripheral circuits is 2% of the power consumed by wire 180nm process Wire length: 5mm

20. Conclusion • Normal serialized bus is proper to data bus • Serialized bus with DDT is proper to address bus • Bus serialization technique decreases power consumption by 30% of conventional in 45nm process • As gate length shrinks, Bus serialization becomes more effective

21. Future Works • Apply to Chip Multiprocessor • Between L1 cache and L2 cache • Additional costs of DDT • Additional circuits and delay

22. Capacitance Model

23. Power increasing by DDT 10 00 10 00 10 10 10 10 1 0 1 0 1 0 1 0

24. Bus Power Model

25. Additional Delay • Conventional bus: 0.17ns • Serialized bus: 0.15ns