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Structural Checking of Voltage-Island and Power Gating Low-Power Logic

971410 吳季恆 971443 張書瑋. Structural Checking of Voltage-Island and Power Gating Low-Power Logic. 摘要.

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Structural Checking of Voltage-Island and Power Gating Low-Power Logic

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  1. 971410 吳季恆 971443 張書瑋 Structural Checking of Voltage-Island and Power Gating Low-Power Logic

  2. 摘要 現今許多IC設計公司所使用的multi-supply voltage island(MSV) 和 power gating (PSO) 低功耗設計技術，即是將晶片上的各個block 分為power-on以及其他可關閉之power domain。而當block停止供電後，會產生訊號不明之問題，因此必須在不同power domain相連之間上插入isolation cell，以避免系統接受到錯誤信號而產生錯誤之狀況。然而這項設計很可能會導致一些常見的故障，因此必須對整個IC的logic netlist structure 和 low power intent加以分析並找出不合規範的設計。不過，傳統基於模擬的驗證方法相當不具彈性同時也缺乏效率，因此不適合於現今的各種低耗設計技術，取而代之的是採取structural checking的方法來改善驗證設計的正確性以及效率。

  3. 簡介 • 問題描述 撰寫一個程式，將讀入之電路依照power intent中的限制，在電路中檢查isolation cell及level shifter的相關資訊，避免整體的電路設計出現不預期的錯誤。 • 軟體功能 能夠讀入電路檔(.v)、標準元件庫(.lib)以及相關的power intent限制條件(.pi)，並針對電路中的isolation cell及levelshifter進行檢查和分析，以提供使用者辨別分析的結果是否有符合原先的需求，將所檢查出的錯誤訊息轉存成Error Report(.rpt)檔案後輸出。

  4. 程式功能圖例

  5. 演算法流程圖 • ISO_1: Power of isolation control pin can be shut-off whileisolation cell is power-on.

  6. ISO_2: Source and destination domains of the isolation cellsare the same.

  7. ISO_3: Isolation instance location does not match isolationrule.

  8. ISO_4: Power domain crossing does not have user-definedisolation cell.

  9. ISO_5: Isolation cell control pin is not connected to thespecified signal.

  10. ISO_6: Isolation instance control polarity is differentthan the specification of isolation rule control.

  11. LS_1: Level shifter input voltage value is different thanspecified by level shifter definition.

  12. LS_2: Level shifter output voltage value is different thanspecified by level shifter definition.

  13. LS_3: Power domain crossing does not have user-defined levelshifter cell.

  14. LS_4: Source and destination domains of the level shiftercells are the same.

  15. 整體程式流程

  16. 程式輸出 • 本程式在完成所有的檢查工作後會將所有的Error Message輸出成Report檔(.rpt)，以下為三個範例 case1: Level shifter input voltage value is different thanspecified by level shifter definition [LS_1] [Level shifter input voltage value is different than specified by level shifterdefinition][Occurrence: 1] - [#1] [Pin 'A' of 'sh0' (module LevLH ) is connected to domain TDON (Power Voltage 1V) Expected voltage domain is 0.8V]

  17. case2: Level shifter output voltage value is different than specified by level shifter definition [LS_2] [Level shifter output voltage value is different than specified by level shifter definition][Occurrence: 1] - [#1] [Pin 'Y' of 'sh1' (module LevLH2 ) is connected to domain TDON2 (Power Voltage 1.2V) Expected voltage domain is 1.5V] case3: Source and receiver signal voltages of level shifter cell are the same in this path [LS_4] [Source and receiver signal voltages of level shifter cell are the same in this path] [Occurrence:2] - [#1] [Level shifter 'sh1' (LevHL) has the same input/output voltage domain in all power modes Input pin driver: u1_1/u_or2/Y Output pin load: u1_2/u_or2/B] [#2] [Level shifter 'sh0' (LevLH) has the same input/output voltage domain in all power modes Input pin driver: u1_1/u_an2/Y Output pin load: u1_2/u_or2/A]

  18. 貢獻及成果簡述 此驗證程式能夠有效及正確的檢查所有的條件限制，在很短的時間及合法使用有效的記憶體空間內，即可以完成所有的步驟，並提供相關的訊息給使用者作進一步的處理。

  19. 參考資料 1. Si2 Common Power Format 1.0/1.1. http://www.si2.org/?page=811 2. The IEEE Standard 1801-2009 3. B. Kappor, et al., "Tutorial: SoC Power Management Verification and Testing," Microprocessor Test and Verification, 2008. Ninth International Workshop on 8-10 Dec. 2008 Page(s):67 – 72 4. Cadence Conformal Low Power Reference Manual

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