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Student Meeting Jose Luis Sirvent PhD. Student 17/02/2014

Beam Secondary Shower Acquisition System: Starting to implement GBT Protocol in Igloo2 and FATALIC as readout candidate. Student Meeting Jose Luis Sirvent PhD. Student 17/02/2014. Igloo2 GBT-FPGA (STD) implementation status Substitute Xilinx IP’s by Microsemi IP’s (Others.. not).

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Student Meeting Jose Luis Sirvent PhD. Student 17/02/2014

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  1. Beam Secondary Shower Acquisition System:Starting to implement GBT Protocol in Igloo2 and FATALIC as readout candidate Student Meeting Jose Luis Sirvent PhD. Student 17/02/2014

  2. Igloo2 GBT-FPGA (STD) implementation statusSubstitute Xilinx IP’s by Microsemi IP’s (Others.. not) • Transceiver with EPCS @ 4.8GBPS: • - A lot of configuration registers • - Big amount of documentation • - Different implemented protocols (not needed) • - Power-Up Initialization needed (HPMS) • - Synchronization issues • - Needed standalone testing and verification

  3. Igloo2 SERDES Testing (Tx part)Different Speeds & Configurations Scope not for eye diagram determination BW 1Ghz, used just for reference  2* Signal Freq = Bit rate Transmission pattern  “10101010101010101010” EPCS @ 1.25Gbps Pre-Configured EPCS @ 2.5Gbps Pre-Configured EPCS @ 4.8Gbps!! Custom Parameters **EPCS : External Physical Coding Sublayer

  4. Igloo2 SERDES Testing (EPCS-4.8Gbps) Looping the lines, TX & RX simulation and start-up sequence

  5. Igloo2 SERDES Testing (EPCS-4.8Gbps) Looping the lines, TX & RX simulation and start-up sequence • Next Step: • Continue validation or data TX/RX in simulations • Start validation with Igloo2 Dev. Kit (Lane1) • Study initialization sequence and look for optimization • Gradual implementation of IP module on Igloo2 GBT-FPGA code • Frame Alignment • GBT encoding/decoding • …

  6. Igloo2 SERDES Testing (TX & RX @ EPCS 4.8GBPS)Working with the Dev. Board and the means it provides Parallel Received Data (20 bits): “11110 00011 11111 1XXXX” Parallel Input Data (20 bits): “111100001111 1111 XXXX” FramePos 3 2 1 0

  7. Igloo2 SERDES Testing (TX & RX @ EPCS 4.8GBPS)Working with the Dev. Board and the means it provides Parallel Received Data (20 bits): “11110 00011 11111 1XXXX” Parallel Input Data (20 bits): “111100001111 1111 XXXX” SERDES Rx Tx FramePos 3 2 1 0 DataRx_0 DataRx_1 … DataRx_19 DataTx_0 DataTx_1 … DataTx_19

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