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Very Large Scale Integration II - VLSI II Verilog HDL Basics Hayri U ğur UYANIK

Very Large Scale Integration II - VLSI II Verilog HDL Basics Hayri U ğur UYANIK ITU VLSI Laborator ies Istanbul Technical University. Outline. Verilog Simulation Setup Language Fundamentals Design Entities Concurrent Statements Data Types and Objects Operators Conditional Constructs

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Very Large Scale Integration II - VLSI II Verilog HDL Basics Hayri U ğur UYANIK

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  1. Very Large Scale Integration II - VLSI II Verilog HDL Basics Hayri Uğur UYANIK ITU VLSI Laboratories Istanbul Technical University

  2. Outline • Verilog Simulation Setup • Language Fundamentals • Design Entities • Concurrent Statements • Data Types and Objects • Operators • Conditional Constructs • Other • Simulation Fundamentals

  3. Verilog Simulation Setup

  4. Language Fundamentals • Design Entities • Concurrent Statements • Data Types and Objects • Operators • Conditional Constructs • Other • Simulation Fundamentals

  5. Design Entities • Only “module” design entity module MODULE1(input1, input_bus, output1, output_bus, inout1); input input1; input [<size-1>:0] input_bus; output output1; output [<size-1>:0] output_bus; inout inout1; SUBMODULE1 U1(submodule1_input1, submodule1_output1); …. endmodule

  6. Concurrent Statements • Statements executed in parallel always @(<sensitivity list>) begin <some combinational or sequential operations>; end assign <combinational operations>;

  7. Data Types and Objects • Logic Values: 0 1 X Z • Numbers: width'radix value • Binary: 8'b10001011 • Octal: 8'o213 • Hexadecimal: 8'h8B • Decimal: 8'd139 • No radix = Decimal 139 • wire, reg: Physical • wire: output of assign block • reg: output of always or initial (test purpose) block • parameter: Somewhat Physical • integer: Mostly Test Purpose

  8. Operators • Bus Operators • Arithmetic Operators • Bitwise Operators • Reduction Operators • Logical Operators

  9. Bus Operators • A = 8'b10001011

  10. Arithmetic Operators • A = 8'b10001011 = 139

  11. Bitwise Operators • A = 8'b10001011

  12. Reduction Operators • A = 8'b10001011

  13. Logical Operators • A = 8'b10001011

  14. if – else if(<Logical Statement1>) begin <Some Operations>; end else if(<Logical Statement2>) begin <Some Operations>; end else begin <Some Operations>; end case case (<Select>) <Value1> : begin <Operations>; end <Value2> : begin <Operations>; end … default: begin <Operations>; end endcase Conditional Constructs

  15. Other • Comments // /* ….. */ • End of statement <Statement>; • Assignments • Blocking (Assignment in order) = • Non-blocking (Assignment in parallel) <= • Timing `timescale <unit>/<precision>

  16. Simulation Fundamentals • Delays # <Number of Units> • Loops repeat, while, for, forever • Simulation Sequence initial begin <Simulation Sequence>; end • System Tasks • File I/O ($fopen, $fwrite, $fscanf.. etc) • Read Memory From File ($readmemb, $readmemh) • Stop Simulation ($stop) • Quit Simulation ($finish)

  17. Loops • Repeat initial begin repeat (30) begin @(posedge CLK); #1 DATA_IN = $random; end end

  18. Loops • While initial begin while (EMPTY==1'b0) begin @(posedge CLK); #1 read_fifo = 1'b1; end end

  19. Loops • For intitial for (i=0; i<15; i=i+1) DATA[i] = 1'b0; end

  20. Loops • Forever initial forever begin CLK = 1'b0; #5 CLK = 1'b1; #5; end

  21. Code Examples module Full_Adder8(A, B, Sum, Carry_Out); input [7:0] A, B; output [7:0] Sum; output Carry_Out; assign {Carry_Out,Sum} = A + B; endmodule

  22. Code Examples module Full_Adder8(A, B, Sum, Carry_Out); input [7:0] A, B; output [7:0] Sum; output Carry_Out; reg [7:0] Sum; reg Carry_Out; always@(A or B) begin {Carry_Out,Sum} = A + B; end endmodule

  23. Code Examples module Full_Adder8_Clock(CLK,A, B, Sum, Carry_Out); input [7:0] A, B; input CLK; output [7:0] Sum; output Carry_Out; reg [7:0] Sum; reg Carry_Out; always@(posedge CLK) begin {Carry_Out,Sum} <= A + B; end endmodule

  24. Code Examples module Test_Full_Adder8_Clock; reg CLK; reg [7:0] A, B; wire [7:0] Sum; wire Carry_Out; Full_Adder8_Clock U1(CLK,A, B, Sum, Carry_Out); initial begin CLK = 0; A = 30; B = 40; #8 A = 20; //8th time unit B = 10; #10 A = 100; B = 100; //18th time unit #10 $finish; end always #5 CLK = ~CLK; endmodule

  25. Code Examples module Shift_Reg_4_Good(CLK, RSTB, D, Q); input CLK, RSTB; input D; output [3:0] Q; reg [3:0] Q; always@(posedge CLK or negedge RSTB) begin if(!RSTB) begin Q <= 4'b0000; end else begin Q[0] <= D; Q[1] <= Q[0]; Q[2] <= Q[1]; Q[3] <= Q[2]; end end endmodule

  26. Code Examples module Shift_Reg_4_Ugly(CLK, RSTB, D, Q); input CLK, RSTB; input D; output [3:0] Q; reg [3:0] Q; always@(posedge CLK or negedge RSTB) begin if(!RSTB) begin Q = 4'b0000; end else begin Q[3] = Q[2]; Q[2] = Q[1]; Q[1] = Q[0]; Q[0] = D; end end endmodule

  27. References • Smith D. J., 1996. HDL Chip Design • Xilinx Help

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