1 / 3

Assignments Documentation Dr Fearghal Morgan

Assignments Documentation Dr Fearghal Morgan. Aim : Capture and implement a digital i mage p rocessing s ystem implemented on the Digilent Xilinx Spartan-3 FPGA development system, controlled by & communicating with host GUI appliedVHDL project overview The project incorporates

Download Presentation

Assignments Documentation Dr Fearghal Morgan

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Assignments DocumentationDr Fearghal Morgan • Aim : • Capture and implement a digital image processing system implemented on the Digilent Xilinx Spartan-3 FPGA development system, controlled by & communicating with host GUI • appliedVHDL project overview • The project incorporates • Digital systems analysis and design • Use of a structured design, documentation, test and implementation methodology • VHDL design entry • VHDL testbench and simulation • VHDL Bus Functional Model (BFM) creation • VHDL Synthesis • FPGA Implementation and hardware test • The following resources are provided: • Template Xilinx ISE project files, template VHDL files, Modelsim macro files • Host serial interface GUI • Digilent Spartan-3 FPGA Hardware Development Module • Xilinx ISE and Modelsim XE EDA tools

  2. Assignment steps Several exercises form part of the larger appliedVHDL project, as follows: Follow assignment instructions to complete each element in sequenceSubmission instructions Project PhasesPhase 1 : displayCtrlr Multiplexed 7-seg display & LED ctrlr Phase 2 : cascadedBCDCntr&displayCtrlr: Cascaded BCD counter connected to displayCtrlr Phase 3 :appliedVHDLV1 CSR r/w, display controller, serial I/O Phase 4 :appliedVHDL CSR r/w, display controller, serial I/O, SRAM r/w controller, SRAM Bus Functional Model (BFM), Datapath controller, DSP function (image processing fn)

  3. appliedVHDL System Design Documentation • Structured Design and Documentation methodology is used to describe the appliedVHDL project. (Link to overview presentation) • Structured design documentation set elements: • Top level Context Diagram (CD) • Process Descriptions • Data Dictionaries (DD) • Data Flow Diagrams (DFDs) • Functional Partitions (at unit and top levels) • Timing Diagrams • Flow charts (Finite State Machine (FSM) descriptions) • Note : alternative design solutions exist to that provided. Adhere to the appliedVHDL design architecture provided though suggest alternatives as the course progresses.

More Related