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Thermal-Driven Multilevel Routing for 3-D ICs

Jason Cong and Yan Zhang ASP-DAC 2005. Thermal-Driven Multilevel Routing for 3-D ICs. Outline. Introduction Problem Formulation and New Challenges the resistive thermal model Multilevel routing with Thermal-Driven Experimental Results Conclusions. Introduction. The advantages of 3D-IC:

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Thermal-Driven Multilevel Routing for 3-D ICs

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  1. Jason Cong and Yan Zhang ASP-DAC 2005 Thermal-Driven Multilevel Routing for 3-D ICs

  2. Outline • Introduction • Problem Formulation and New Challenges • the resistive thermal model • Multilevel routing with Thermal-Driven • Experimental Results • Conclusions

  3. Introduction • The advantages of 3D-IC: • Studies [1] demonstrate a potential performance improvement of up to 65% by transferring a placement from 2-D to 3-D and eliminating long interconnects. • [1]:3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration.

  4. Introduction • The drawback of 3D-IC: • heat dissipation • The devices are more packed, which results in higher power density. • the insulating dielectric layers between the device layers have much lower thermal conductivities than silicon.

  5. Problem Formulation and New Challenges • Thermal-Driven 3-D Routing Problem Formulation: • Objective: • the weighted cost of wirelength and the total TS-via(Through-the-silicon vias) number is minimized.

  6. Problem Formulation and New Challenges • Thermal-Driven 3-D Routing Problem Formulation: • Inputs: • 1. the target 3-D IC technology, including design rule, height and thermal conductivity of each material layer, • 2. a 3-D circuit placement or floorplan[24] result with whitespace reserved between blocks for interlayer interconnects, • [24]:A Thermal-Driven Floorplanning Algorithm for 3D Ics(ICCAD2004) • 3. a given maximum temperature T0 , e.g. 80oC, • 4. the connecting rule

  7. The resistive thermal model • 1.Basic Thermal Calculation and Assumption • 2.Compact Thermal Resistive Model for 3-D IC

  8. The resistive thermal model • Basic Thermal Calculation and Assumption • We assume all heat sources (blocks) are of constant power density. • The steady-state on-chip temperature satisfies the following equation [9], k(x, y, z) ▽ 2T(x, y, z) + g(x, y, z) = 0.

  9. The resistive thermal model • Compact Thermal Resistive Model for 3-D IC • we chose to make use of a compact thermal resistive model proposed by Wilkerson, et al. [11], which explicitly models the thermal effects of the vias.

  10. Multilevel routing with Thermal-Driven • Multilevel Routing • An Enhanced Multilevel Routing System[23,iccad2002]

  11. Multilevel routing with Thermal-Driven • A multilevel routing scheme is composed of a recursive coarsening, an initial routing and a recursive refinement process.

  12. Multilevel routing with Thermal-Driven • TS-via Modeling • All TS-vias in each tile are lumped together at the center of that tile.

  13. Multilevel routing with Thermal-Driven • TS-Via Planning • given a planning window PW, for TS-vias {vi}, i = 1,… ,m, in PW, and tiles {Tj}, j = 1,…, n, covered by PW, with position (xj , yj) and capacity cj , assign each TS-via to one of the tiles, so that the total TS-via number assigned to each tile Tj does not exceed its capacity cj , and the wirelength and the maximum temper ature is minimized.

  14. Multilevel routing with Thermal-Driven • TS-via number distribution • TS-via number distribution step is carried out to assign the dummy TS-vias to the tiles. • Signal TS-via and dummy TS-via assignment • try to optimize wirelength.

  15. Multilevel routing with Thermal-Driven • TS-via number distribution • nv(j): a TS-via number is assigned to each tile Tj in PW. • max(T(j)): the resulting maximum tile temperature in PW. • Δ T(j): is the temperature difference of Tj and the device layer tile immediately below Tj.

  16. Multilevel routing with Thermal-Driven • TS-via number distribution • Objective: • we assign a TS-via number nv(j) to each tile Tj in PW, so that the resulting maximum tile temperature max(T(j)) in PW is minimized.

  17. Multilevel routing with Thermal-Driven • Signal TS-via and dummy TS-via assignment • signal TS-vias are first assigned to each tile according to the wirelength cost. The problem can be formulated as a min-cost max-flow problem.

  18. Multilevel routing with Thermal-Driven • Signal TS-via and dummy TS-via assignment • Ex: assigning six TS-vias, v1, ..., v6 to four tiles, T1, ..., T4. v1 T1 v2 T2 t s v3 v4 T3 v5 T4 v6

  19. Multilevel routing with Thermal-Driven • Signal TS-via and dummy TS-via assignment • Ex:

  20. Experimental Results

  21. Conclusions • Also, because of the importance of TS-vias in heat dissipation, early thermal planning, such as during 3-D floorplanning or placement, can also improve results in both temperature and wirelength.

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