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A Thermal-Driven Floorplanning Algorithm for 3D ICs

A Thermal-Driven Floorplanning Algorithm for 3D ICs. Jason Cong, Jie Wei, and Yan Zhang ICCAD 2004. OUTLINE. Introduction Problem formulation 3D thermal-driven floorplanning algorithm Experimental results Conclusion. Introduction. Motivation for 3D ICs Reduce interconnect delays.

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A Thermal-Driven Floorplanning Algorithm for 3D ICs

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  1. A Thermal-Driven FloorplanningAlgorithm for 3D ICs Jason Cong, Jie Wei, and Yan Zhang ICCAD 2004

  2. OUTLINE • Introduction • Problem formulation • 3D thermal-driven floorplanning algorithm • Experimental results • Conclusion

  3. Introduction • Motivation for 3D ICs • Reduce interconnect delays • Source: Proc of the IEEE, 2001

  4. Introduction • Different 3D technologies • Chip level integration • Block level integration (this paper focus) • Cell level integration(over 500k) Cell level Block level Chip level

  5. Introduction • The current thermal models: • Numerical computing methods such as FEM(Finite Element Method)[8] and FDM(Finite Difference Methods)[21][22] • Compact resistive network[20] • Simplified closed-form formula[6][14] • Time-consuming :1>2>3 • Accurate:1>2>3

  6. Problem formulation

  7. Problem formulation

  8. 3D floorplanning algorithm • 2D floorplanning algorithm: • sequence pair[18],BSG[16],B*-Tree[4],O-Tree[11],CBL[12],TCG[17],etc. • 3D floorplanning algorithm[CBA(Combined Bucket and 2D Array)]: • 2D floorplanning algorithm + a bucket structure • 2D floorplanning(TCG[17]): • is used to represent each layer • A bucket structure: • is posed on the circuit stack

  9. 3D floorplanning algorithm • TCG(Transitive Closure Graphs [DAC 2001]): • two constraint graphs : horizontal and vertical graph.

  10. 3D floorplanning algorithm • A bucket structure: • IB(i) : In each bucket i, indexes of the blocks that intersect with the bucket are stored. • IBT(j) : each block j stores indexes to all the buckets that overlap with the block. Die3 Die2 Die1

  11. 3D floorplanning algorithm • A bucket structure: 3DFP of a 2-layer 7-block floorplan

  12. 3D floorplanning algorithm • SA(Simulated Annealing): • Cost = a*nwl+b*narea+c*nvc+d*CT • Solution Perturbation: • Rotation • Swap • Reverse • Move • Interlayer swap • Z-neighborswap • Are based on the concept of z-axis neighbor • Z-neighbor move • Are based on the concept of z-axis neighbor

  13. 3D floorplanning algorithm • Z-axis neighbor: • The definition is based on the bucket structure. • The z-axis neighbor of a given block j. • Zn(j):the block k in B(j) with the minimum neighboring cost zc(j,k)=a*|Ak-Aj|+b*dist(k,j) • dist(k,j)=|xk-xj|+|yk-yj| • Z-neighbor swap:is to swap a block with its z-axis neighbor. • Z-neighbor move: Bi is moved from its own layer li to the layer lj where Bj locates. Bi is positioned adjacent to Bj at either top or right side.

  14. 3D floorplanning algorithm After a z-neighbor move operation on d After a z-neighbor swap operation on b and f

  15. 3D floorplanning algorithm • Thermal model: • Compact resistive thermal model[24] • Simplified Closed-form thermal model • Vertical Heat Flow Analysis • Horizontal Heat Flow Analysis

  16. P 5 5 R 5 P 4 4 R 4 P 3 3 R 3 P 2 2 R 2 1 P 1 R 1 R b + - - - 3D floorplanning algorithm • Vertical Heat Flow Analysis • Considering only 1-D heat flow, minimize the Elmore delay like formula • Horizontal Heat Flow Analysis • Even out the temperature distribution on the chip, avoiding “hotspot”

  17. Experimental results • With the new operations, 3D-FP can improve the area by 5% and wirelength by 3%

  18. Experimental results • 3D-FP-T can greatly reduce the temperature by 56% with 9.7x runtime

  19. Experimental results • 3D-FP-T-Fast can reduce the temperature by 40% with 1.8x runtime • 3D-FP-T-Hybrid can reduce the temperature by 50% with 3.2x runtime

  20. Experimental results - by commercial FEM based tool (CFD-ACE+)- ami33 benchmark with 33 blocks and 4 layers

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