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Energy-oriented Retargetable SDK

Energy-oriented Retargetable SDK. SangJi University Kwangman Ko 2011. 11. 5. contents. Research Motivations ADL-driven SDK Generation ??? Related works and trends EXPRESSION 1 LISA 2 SoarGen 3 Energy-oriented retargetable SDK(EoSDK) References and Interesting Sites.

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Energy-oriented Retargetable SDK

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  1. Energy-oriented Retargetable SDK SangJi University Kwangman Ko 2011. 11. 5.

  2. contents • Research Motivations • ADL-driven SDK Generation ??? • Related works and trends • EXPRESSION1 • LISA2 • SoarGen3 • Energy-oriented retargetableSDK(EoSDK) • References and Interesting Sites DGU PL Lab. Workshop, 2011.

  3. Research Motivations • Embedded system designers faced with the some tasks • shrinking Time-to-Market cycles. • reduced processor life-time • high performances , application specific processor • low power & energy consumptions • rapidly exploring and evaluating different architecture • Retargetable SDK Generation Techniques • retargetable {optimizing} compiler • retargetable assembler • Retargetable debugger • retargetable {instruction-set, cycle-accurate} simulator • … DGU PL Lab. Workshop, 2011.

  4. ADL-driven SDK Generation • Automatic Software Development Kits generation • A language-based design methodology • ADLs: Architecture Description Languages Architecture Spec. ADL Specification Hardware Prototype Toolkit Generation Test Programs DGU PL Lab. Workshop, 2011.

  5. Architecture Description Language; ADL. capture the structure( hardware components and their connectivity ) and the behavior( instruction-set ) of architectures. Architecture Description Language Simulator Generator Compiler Generator Compiler Simulator binary results *.c DGU PL Lab. Workshop, 2011.

  6. ADL catagories DGU PL Lab. Workshop, 2011.

  7. Structuring of ADL • Behavioral part • composed of operation semantics, operation addressing mode, assembly mnemonics, binary encoding • mainly used for compiler(instruction selector), assembler, simulator(functional accurate) • Structural part • composed of hardware resources like memory, registers, register files, functional units • mainly used for compiler(register allocator) DGU PL Lab. Workshop, 2011.

  8. Related works: EXPRESSION • EXPRESSION • design and developed by UC Irvine, 1998 to 2007. • language supporting architectural design space exploration • EXPRESSION ADL • A simple LISP-like syntax to ease specification and enhance readability • EXPRESS • automatic generation of a retargetable compiler • SIMPRESS • automatic generation of a retargetable simulator • Cycle-accurate simulator & based on interpretive simulation. DGU PL Lab. Workshop, 2011.

  9. DGU PL Lab. Workshop, 2011.

  10. Expression ADL: 6 Sections • Operations Specification • Instruction Description • Operation Mappings • Components Specification • Pipeline and Data-transfer Paths Description • Memory Subsystem DGU PL Lab. Workshop, 2011.

  11. Operations Specification • describes the Instruction-Set of the processor • operation is described in terms of its OPCODE, OPERANDS, BEHAVIOR, and INSTRUCTION FORMAT. ( opcodeadd ( operadns (s1 reg) (s2 reg/int16) (dst reg) ) ( behavior dst = s1 + s2 ) ( format 000101 dst(25-21) s1(21-16) s2(15-0) ) ) ( opcodestore ( operands (s1 reg) (s2 int16) (s3 reg) ) ( behavior M[s1+s2] = s3 ) ( format 00101 s3(25-21) s1(21-16) s2(15-0) ) ) DGU PL Lab. Workshop, 2011.

  12. Operation Mappings • user specifies information needed by Instruction Selection and architecture-specific optimizations of the compiler. • Represents the mapping of an (sequences of) operations(s) to another (sequences of) operations(s). ( ( GENERIC ( IADD dst src1 src2 ) ) ( TARGET ( ADD dst src1 src2 ) ) ) ( ( GENERIC ( IMUL dst src1 #2 ) ) ( TARGET ( ADD dst src1 src1 ) ) ) DGU PL Lab. Workshop, 2011.

  13. Related works: LISA • LISA • Commercialized retargetable SDK Generation system • A language designed for the formalized description of programmable architecture. • generating SDKs for a broad range of architectures • RISC, VLIW, NPU, DSP, and ASIP • allowing the usage of C for the instruction behavior description • C-like syntax. DGU PL Lab. Workshop, 2011.

  14. LISA description • Resource declarations • The storage objects of the hardware architecture • capture the state of the system and which can be used to model the limited availability of resources for operation access. • Operations • the basic objects in LISA • Represent the designer’s view of the behavior, the structure, and the instruction set of programmable architecture. DGU PL Lab. Workshop, 2011.

  15. Related works: SoarGen DGU PL Lab. Workshop, 2011.

  16. SoarDL : an ADL of SNU • Language for Architecture Description • Automatic generation of compiler, assembler, and linker • Structural Description + Behavioral Description + Conventions • Structural description : registers and memory structure • Behavioral description : address modes and instruction sets DGU PL Lab. Workshop, 2011.

  17. SoarDL extension SoarDL description SoarDL Parser Processor Model Machine Dependent File Generator compiler assembler linker ISS CAS DGU PL Lab. Workshop, 2011.

  18. Energy-oriented retargetableSDK(EoSDK) DGU PL Lab. Workshop, 2011.

  19. DGU PL Lab. Workshop, 2011.

  20. Preliminary works • An Energy-oriented Retargetable Simulator for Instruction-Set Architecture, International Conf. of Embedded Systems and Applications, 2011. • 에너지 소비 모니터링을 위한 재목적 인스트럭션-셋 시뮬레이터(Retargetable Instruction-Set Simulator for Energy Consumption Monitoring), 한국멀티미디어학회논문지, Vol. 14, No. 3, March 2011. • An Energy-oriented Retargetable Simulator for Instruction-Set Architecture, 2010 NRF Visiting Professor Program Final Report, December 2010. • ADL로부터 에너지-지향 인스트럭션 스케줄링을 위한 예약 테이블 생성 기법(Generation Technique of Reservation Tables for the Energy-oriented Instruction Scheduler from ADL Descriptions),한국정보기술학회논문지, Vol. 8, No. 10, September 2010. • 클래스-기반 아키텍처 기술 언어의 설계 및 검증(Design and Verification of the Class-based Architecture Description Language), 한국멀티미디어학회논문지,Vol. 13, No. 7, July 2010. • Development of the Retargetable Tool Suite for Embedded Software, International Journal of Software Engineering and Its Applications, Vol. 3., N0. 2, March 2009. • ADL Design • Design of ADL with Instruction Level Energy Consumption Attributes DGU PL Lab. Workshop, 2011.

  21. Energy-oriented Compiler: eCompiler • Energy efficient instruction scheduling strategies ? • Instruction Level List Scheduling Technique for the Optimized Energy Consumption, To be published. • Energy efficient optimizations strategies ? DGU PL Lab. Workshop, 2011.

  22. Energy-oriented Simulator: eSimulator • Simulation level ? • Simulation speed, accuracy, … • Energy estimation and tracing simulation engine • Simplescalar, Simplepower, Wattch, … DGU PL Lab. Workshop, 2011.

  23. References and Interesting Sites • EXPRESSION, http://www.ics.uci.edu/~express/ • LISA: http://www.iss.rwth-achen.de/Projekte/Tools/lisa/index.html • SoarGen, http://optimizer.snu.ac.kr • Prabhat Mishra, Nikil Dutt, "Architecture Description Languages for Programmable Embedded Systems", in System-on-Chip: Next Generation Electronics(Editor: Bashir M. Al-hashimi), The Institution of Electrical Engineers, pages 187∼220, 2006. • Anupam Chattopadhyay, Heinrich Meyr, Rainer Leupers, "LISA: A Uniform ADL for Embedded Processor Modeling, Implementation and Software Toolsuite Generation" in Processor Description Languages(Editor: Prabhat Mishra, Nikil Dutt), Morgan Kaufmann, pages 95∼132, 2008. • M. Hohenauer, Retargetable Code Generation based on an Architecture Description Language, Ph. D. Thesis, RWTH Aachen University, 2009. • Y. N. Srikant, "Energy-Aware Compiler Optimizations", in The Compiler Design Handbook: Optimizations and Machine Code Generation 2nd Edition(Editor: Y. N. Shikan, K. A. Vardhan), CRC Press, pages 235∼265, 2008. • P. Mishra, N. Dutt, "Architecture Description Language(ADL)-driven Software Toolkit Generation for Architectural Exploration of Programmable SOCs", ACM Trans. on Design Automation of Electronics Systems, Vol. 11, No. 3, pages 626∼658, 2006. • Minwook Ahn, SoarGen: A User Retargetable Compiler in the Design of Embedded Systems, Ph. D. Thesis, Seoul National University, 2009. • Chingren Lee, Jenq Kuen Lee, Tingting Hwang, and Shi-Chun Tsai, "Compiler Optimization on VLIW Instruction Scheduling for Low Power", ACM Trans. on Design Automation of Electronic System, Vol. 8, No. 2, pages 252∼268, 2003. • A. Parikh, Soontae Kim, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, "Instruction Scheduling for Low Power", Journal of VLSI Signal Processing, Vol 37, pages 129∼149, 2004. • I. Kadayif, M. Kandemir, G. Chen, N. Vijaykrishnan, M. J. Irwin, A. Sivasubramaniam, “Compiler-directed high-level energy estimation and optimization”, ACM Transactions on Embedded Computing System, Vol. 4, Issue 4, 2005. • Meikang Qiu, Meiqin Liu, Hao Li, Hung-Chung Huang, Wenyuan Li, Jiande Wu, “Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture”, Journal of Signal Processing Systems, Vol. 57, Num. 3, 2009. • Kwangman Ko, "An Energy-oriented Retargetable Simulator for Instruction-Set Architecture", 2010 NRF Visiting Professor Program Final Report, December 2010. • nML Description of the TCT Core Processor: http://www.retarget.com/nml, March, 2008. DGU PL Lab. Workshop, 2011.

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