Hard IP Reuse – a Survey

1. Hard IP Reuse – a Survey Shmuel Wimer Bar Ilan University, School of Engineering Hard IP Reuse

2. Outline • Design and Market Considerations • Hard and soft IP reuse • Intel’s Tick / Tock • Design consideration • Layout Migration in Work • Transistor, cell and block compaction • Delay and circuit considerations • Late process changes / updates • Design For Manufacturability • Layout Migration Algorithms and Techniques • Hierarchy in layout • Visibility, compaction and positive cycles • Cell based migration Hard IP Reuse

3. Part IDesign and Market Considerations Hard IP Reuse

4. Hard Vs. Soft IP Reuse • Hard IP reuse is transforming the polygons of old taped-out data into new process technology • Net list doesn’t change • Circuit changes are limited to resizing only • Suitable for custom design • Soft IP reuse is using the same RTL of old design with a new target library design in any technology • Architecture, Verilog and RTL are not changing • Net list is changing • Layout is done from scratch • Future is questionable as FPGA usage is spreading Hard IP Reuse

5. Advantages of Hard IP Reuse • Fabless companies • Lower design cost • Better Mfg. Shopping, few sources • Competition, TTM • Intel’s drive • System Integration, SoC • Manufacturing cost, volumes • Performance enhancement • Competition, TTM Hard IP Reuse

6. Intel’s Tock / Tick Strategy Hard IP Reuse

7. Intel Architecture Roadmap Hard IP Reuse

8. Tock Vs Tick Design • Tock • New Architecture, design implementation and layout • Matured process technology • New CAD tools and DA flows • Large design team and Long duration • Tick • Stable design, only few new features • New process technology • Maximizing soft and hard IP reuse • Smaller design team and shorter period Hard IP Reuse

9. Design Reuse at Intel • Long history of successful projects at Intel • 2-year cadence • Banias 130nm => Dothan 90nm (Centrino) – 2001 • Dothan 90nm => Yonah 65nm (Centrino) – 2003 • Prescott 90nm => CedarMill 65nm (Pentium IV) – 2003 • Merom 65nm => Penryn 45nm (Core 2 Dou) – 2005 • Nehalem 45nm => Westmere 32nm – 2007 • SandyBridge 32nm => IvyBridge 22nm – 2009 Hard IP Reuse

10. Design Reuse at Intel – Past • Emphasize on layout migration • Yielded nominal device speedup minus 3% to 6% • Was okay for 35% speedup across process generations • 65nm to 45nm was very tough • In-house development of migration flows • Core compaction technology purchased from vendor • Migrate and reuse polygons by “classical” compaction • Straight forward but not fully exploiting new process, one shot • Saved lot of mask designer resources • Shorter TTM • 3Q to 5Q design duration compared to 8Q to 9Q in re-design Hard IP Reuse

11. Design Reuse – Present and Future • Migrate entire design rather than layout • Optimize design factors as timing and power • Circuit optimization • Cell resizing • Interconnect optimization (driver – interconnect – receiver) • Layout optimization • Migrate cell library, trading off scaling and cell performance • Cell-based: Nehalem to Westmere, SandyBridge to IvyBridge • Xscale (Intel) to 90nm TSMC (Marvell) • Much less process dependent than polygon migration • Flexible for further changes and migrations Hard IP Reuse

12. Design Optimizations in Migration • Power and Timing tradeoffs • Resizing and re-spacing optimization techniques • Interconnect specs Vs. post optimization • How much improvement is expected? • 5% speedup • 5% dynamic power reduction • Reliability and DFM • Noise immunity Hard IP Reuse

13. 65nm / 45nm LO 45nm DR netlist + sizing compaction engine (polygon or cell-based) Intel’s proprietary SW LO quality guidelines interconnect width and space OPC guidelines PWR grid resizing 45nm LO Typical Layout Migration Flow Hard IP Reuse

14. Challenges in Hard IP Reuse • Significant reduction of DE and MD effort • Combination of CAD tools, design flows and managerial decisions • Fast TTM • More area efficiency • State-of-the-art manufacturing process technologies • Discrete design rules • Very complex DFM rules • Migration-based process design • Combine process simulation with layout migration tools • Yield and reliability enhancement • Analog design re-use Hard IP Reuse

15. Part IILayout Migration in Work Hard IP Reuse

16. Transistors and Metal Comparison 90nm 65nm Hard IP Reuse

17. Transistors and Metal Comparison 65nm 90nm Hard IP Reuse

18. 130nm Cell Comparison 90nm Hard IP Reuse

19. 130nm drawn 212u X 103u Block Comparison 90nm drawn 112u X 54u Hard IP Reuse

20. Timing Delivery of Migration • 65nm Vs. 90nm nominal speedup 26% • Cycle time speedup set to 22% (Simulation comparison) • Yonah cycle 360p Vs. Dothan cycle 460p • LO Migration timing speedup measure: % of delay speedup that 80% of paths meet • Migration yielded 19% speedup in above measure • This is less than desired • Similar degradation observed in Dothan Hard IP Reuse

21. Maintaining PWR Grid • 1st migration scaling • M2 0.32u to 0.32u • M3 0.88u to 0.77u (max width violation) • M4 0.84 to 0.42u (with fixing) • Tight monitoring of scaling success • 2nd migration • slotted M3 to 0.33u + 0.11u space + 0.33u • Introduced large vias Hard IP Reuse

22. original drawing gate degrades in manufacturing fix by new design rules Late Changes in DR’s Hard IP Reuse

23. Process change: small contact large via large contact small via n-diff metal1 via poly metal2 contact Late Changes in DR’s (Cont’d) Hard IP Reuse

24. Late Changes in DR’s (Cont’d) 65nm after changing 65nm Hard IP Reuse

25. Benefits of LO migration • Low design effort, short schedule (see Dothan Vs. Tualatin) • Stable design, no escapees • Fast timing convergence • Design can start early, best utilization of HR • Flexibility for later changes in process • Raw migration of 90nm to 65nm • MD’s make first cleanup • Later 65nm to 65nm migration Hard IP Reuse

26. Part IIILayout Migration Algorithms and Techniques Hard IP Reuse

27. Hierarchy in Layout Hard IP Reuse

28. Non Uniform Hierarchical Migration Hard IP Reuse

29. before: 45 nm after: 32 nm / 0.7 Hard IP Reuse

30. before: 45 nm Hard IP Reuse

31. after: 32 nm / 0.7 Hard IP Reuse

32. Relations Between Layout Objects • Relations are captured in graph • Sometimes called constraints graph • Graph describes technology rules and other design constrains • Proximity relations due to noise and delay considerations • Alignment of layout pieces called pitch matching • Adjacency relations never change • No swapping of objects • 1D Compaction can still change orthogonal adjacency relations • Design rules are captured in visibility graph • Planar by definition • Design rules Transitivity enables transitive reduction of visibility graph Hard IP Reuse

33. Visibility graph of cell layout • Nodes are cells` center lines • Arc represents cells visible to each other • Arc weights represent target cell size and spacing between cells • Visibility graph of polygonal layout • Nodes are polygon edges • Arc represent polygon interior (material) and spacing between polygons visible to each other • Arc weights represent width and space of polygons • Visibility graph of symbolic layout • Nodes are sticks skeletons (e.g. wires, vias) or centerline of encapsulated polygons (e.g. transistors) Hard IP Reuse

34. Visibility Graph in Cell Layout Hard IP Reuse

35. Visibility Graph in Polygonal Layout Hard IP Reuse

36. Generation of Reduced Visibility Graph • Alternative A: • Find visibility graph • Left-to-right or bottom-to-top sweep-line algorithm • Remove transitive edges from graph • Equivalent to matrix multiplication • Alternative B: • Take advantage of problem being interval graph • Intervals approached by sweep-line are stored in ordered tree • Transitive edges are removed during scanning whenever adjacency relation of two leaves is broken by insertion of new node Hard IP Reuse

37. Hard IP Reuse

38. x0 x1 x2 x3 x4 x5 Cycles in Edge-based Compaction Hard IP Reuse

39. A -A Smin Wmin Smin /2 Smin /2 Wmin x0 x1 x2 x3 x4 x5 Inequalities impose a linear programming problem Inequalities are translated into constraint graph. Edge locations can be obtained by finding longest paths. Feasible solution exists if there’s no positive cycle in constrained graph. Hard IP Reuse

40. Bellman-Ford Algorithm Hard IP Reuse

41. Correctness of Bellman-Ford Algorithm Hard IP Reuse

42. Hard IP Reuse

43. 5 g u v h b -16 6 a j -8 5 -3 z -22 -4 f i 7 c e d 9 x y Graph edges are labeled a, b, …, I, j according to their order in data structure. Find longest path from z to all vertices. Report whether positive cycle exists. Initialization -∞ -∞ 0 -∞ -∞ Hard IP Reuse

44. i = 1 5 g u v 6 -∞ 11 -∞ h b -16 6 a j -8 5 -3 0 z -22 -4 f i 7 c e d 7 -∞ -∞ 9 x y Hard IP Reuse

45. 5 g i = 2 u v 17 6 11 h b -16 6 a j -8 5 -3 0 z -22 -4 f i 7 c e d 11 20 7 -∞ 9 x y Positive cycles do not exist. Longest path spanning tree is obtained from parent nodes. Hard IP Reuse

46. 0 V1 0 1 V2 0 1 -1 1 V5 V0 0 0 4 0 5 -5 0 -6 V3 -1 5 6 V4 0 Difference Constraints and Longest Paths Hard IP Reuse

47. Hard IP Reuse

48. Bellman-Ford algorithm can therefore solve difference equation system of n variables and m equations in O(n(n+m)) = O(n2 + mn) time complexity. Bellman-Ford can be modified for difference equations specific case to yield O(mn) time complexity. Hard IP Reuse

49. Overview of Cell-Based Hierarchical Interconnect Migration Five-step graph contraction procedure • Flatten layout visibility graph • Define cell call order tree T • Merge cell instances within parents in bottom-up T order • Stop if positive cycle exists, continue otherwise • Eliminate merged cells within parents in bottom-up T order Positioning of interconnects within their templates • Top-down linear programming solution by T order • Feasibility is guaranteed by graph contraction invariance Hard IP Reuse

50. Assumptions • All cells sizes are known and must be adhered • Defined by bottom-up cell-based placement stage. • Outcome of descendant cells sizes and interconnect scaling, specs and estimates. • Position of son cells within parents must be adhered • Same reasons as above • Infeasibility incurring at routing migration is resolved by: • Resizing of migrated cells • Repositioning of son cells • Relaxing interconnect rules and constraints • Left for later manual fixes by circuit and mask designers • Interconnect migration re-invoked • Cell migration / placement – interconnect migration iterations Hard IP Reuse