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CPU Design Project

CPU Design Project. Christopher Brown Fall 2010, ELEC 5200. Overview. Multi-cycle processor 16-bit instructions 16 registers Intel-style instruction set. Registers. AT - Assembler Temporary NULL - Readonly, always 0x0000 FULL - Readonly, always 0xFFFF

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CPU Design Project

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  1. CPU Design Project • Christopher Brown • Fall 2010, ELEC 5200

  2. Overview • Multi-cycle processor • 16-bit instructions • 16 registers • Intel-style instruction set

  3. Registers • AT - Assembler Temporary • NULL - Readonly, always 0x0000 • FULL - Readonly, always 0xFFFF • R0 to R6 - General purpose, maintained across subroutines • T0 to T3 - General purpose, not maintained across subroutines • SP - Stack pointer, for use with pseudo-instructions such as push and pop • IP - Instruction pointer, always points to the next instruction

  4. Instruction Set • Jumps - JMP, JG, JNLE, JGE, JNL, JL, JNGE, JLE, JNG, JE, JNE • Memory - MOV • Arithmetic - ADD, SUB • Bitwise - XOR, AND, OR • Other - NOP, HLT

  5. Jumps • 8-bit relative operand • Flow determined by Sign, Ovrflw, and Zero control flags • 11 varieties: • 1 unconditional • 6 conditional • 4 pseudo

  6. Memory • Uses register indirect addressing only • MOV (srcR), destR • Loads the contents of memory at the address stored in srcR to the register specified by destR. • MOV srcR, (destR) • Stores the contents of srcR to the memory address stored in destR.

  7. Arithmetic • ADD and SUB • 2 variants of each • ADD/SUB regR, destR • Add or subtract the contents of regR from destR, storing the result in destR. • ADD/SUB immed8, destR • Add or subtract immed8 from destR, storing the result in destR. • Updates Sign, Ovrflw, and Zero control flags.

  8. Bitwise • XOR, AND, and OR • XOR/AND/OR regR, destR • Performs a binary operation between regR and destR, storing the result in destR. • Updates Sign and Zero control flags.

  9. Other • NOP • It does nothing. • HLT • Puts the control unit into a halted state • The only way to continue execution is through a reset

  10. Pseudo-Instructions • PUSH regR • SUB 1, SP • MOV regR, (SP) • POP regR • MOV (SP), regR • ADD 1, SP • RET • MOV (SP), IP ; POP IP • ADD 1, SP • CALL relM8XOR AT, ATADD IP, ATADD 4, ATSUB 1, SP ; PUSH ATMOV AT, (SP)JMP relM8

  11. Data-Path

  12. Control Unit • Finite-state-machine • Moore machine - Outputs depend solely on the current state • 8 unique states • Also maintains 3 internal flags: Sign, Ovrflw, and Zero

  13. Control Unit

  14. Questions?

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