1 / 10

CPU Design-Project

CPU Design-Project. Multicycle Datapath with Finite State Machine as Control Unit. N.S.V Ravi Tej Uppu. Core Instruction set:-. Register Name, Number, Use:. Basic Instruction Formats:. o/p’s Control Op(3-0). PCSource. PCWriteCond. ALUop. PCWrite. ALUSrcB. IorD.

phyre
Download Presentation

CPU Design-Project

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. CPU Design-Project Multicycle Datapath with Finite State Machine as Control Unit N.S.V Ravi Tej Uppu

  2. Core Instruction set:-

  3. Register Name, Number, Use: Basic Instruction Formats:

  4. o/p’s Control Op(3-0) PCSource PCWriteCond ALUop PCWrite ALUSrcB IorD ALUSrcA 2 1 0 Mem Write RegWrite MemtoReg Regdst IRWrite Inst(0-11) & PC(12-15) rs Read reg 1 read data 1 Read reg 2 Reg-file Write reg read data 2 Write data 1 mux 0 Inst(15-12) Instruction(11-8) Instruction(7-4) (Inst Reg) Instruction(4-0) zero A PC rt ALU-op Address Memory Mem data Write data 1 mux 0 1 mux 0 rd B 3 2 1 0 1 -1 Multicycle Datapath with Control unit: 1 mux 0 Sign Extend Memory Data Register

  5. Instruction Decode Instruction Fetch ALUSrcA=0 IorD=0,IRwrt ALUSrcB=01 ALUOp=000 PCwrite=1 PCSource=00 ALUSrcA=0 ALUSrcB=10 ALUop=000 0 1 Start (op=‘lw’)or(op=‘sw’) op = R-type Mem Addr Comp Op=beq Op=‘jmp’ Jmp Comp Exec ALUSrcA=1 ALUSrcB=00 AlUop=000 Branch Comp 2 ALUSrcA=1 ALUSrcB=00 ALUop=011 PCwritecond PCSource=01 ALUSrcA=1 ALUSrcB=00 ALUop= opcode(2-0) 8 6 9 PCwrite PCSource=10 MemAccs MemAccs IorD=1 3 R-type Comp Memwrite IorD=1 5 RegDst=1 Regwrite Memtoreg=0 7 Finite State Machine Control: Mem Read Comp 4 RegDst=0 Regwrite MemtoReg=1

  6. Defining The Control Signals:

  7. Test Program:

  8. - Make changes in the core instruction set and add instructions like (a) Jump register (b) Shift left logic -Implement the control unit as a Micro Computer using: (a) Micro Instructions (b) Microprogramming. -Make effective use of the registers defined. Conclusion: The above designed CPU can execute a sequence of instructions which include R-type, Data transfer, branching etc., while its operations for programs which include functions is to be tested. Future modifications:

  9. Questions

  10. Thank you!

More Related