3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled Digital Circuits

1. 3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled Digital Circuits Rajesh Garg Sunil P. Khatri Department of ECE Texas A&M University College Station, TX

2. Outline • Background and Motivation • Previous Work • Simulation Setup • Results and Discussions • Circuit-level hardening guidelines • Model for Charge collected • Conclusions

3. Charge Deposition by a Radiation Particle • Radiation particles - protons, neutrons, alpha particles and heavy ions • Reverse biased p-n junctions are most sensitive to particle strikes • Charge is collected at the drain nodethrough drift and diffusion • Results in a voltage glitch at the drain node • System state may change if this voltage glitch is captured by at least one memory element • This is called an SEU • May cause system failure Radiation Particle VDD G S D _ + n+ n+ Depletion Region + _ + _ E _ + _ E + VDD - Vjn _ + _ + _ + p-substrate B

4. Radiation Strike Model • Charge deposited (QD) by a radiation particle is given by where: Lis the Linear Energy Transfer (MeV-cm2/mg) t is the depth of the collection volume (mm) • A radiation particle strike is modeled by a current pulse as where: Qcoll is the amount of charge collected (assumed Qcoll = QD in worst case analysis) tais the collection time constant tb is the ion track establishment constant • The radiation induced current always flows from n-diffusion to p-diffusion Q = 0.1pC ta = 150ps tb = 50ps

5. Radiation Particle Strikes • Radiation particle strike at the output of INV1 • Implemented using 65nm PTM with VDD=1V • Radiation strike: Q=100fC, ta=200ps & tb=50ps Models Radiation Particle Strike

6. Motivation • Modern VLSI Designs • Vulnerable to noise effects- crosstalk, SEU, etc • Single Event Upsets (SEUs) or Soft Errors • Troublesome for both memories and combinational logic • Becoming increasingly problematic even for terrestrial designs • Applications demand reliable systems • Need to efficiently design radiation tolerant circuits

7. Motivation • Power is becoming a major issue • Low power/energy solutions are desired for SoCs, microprocessors, etc • Both Pdyn and Plkgdecrease atleast quadratically with decreasing supply voltages • Decrease the supply voltage in the non-critical parts • Dynamic voltage scaling (DVS) is extensively used to meet variable speed/power requirements • Sub-threshold circuits are also becoming popular to implement extremely low power systems • Useful for applications which can tolerate large delay

8. 3D Simulations of Radiation Strikes • Reliability of DVS and sub-threshold circuits important for the reliability of VLSI systems • Need to analyze the effects of radiation strikes on such circuits • Harden the circuits based on the results of this analysis • SPICE cannot be used for this analysis • The effect of a radiation particle strike is modeled, not the radiation strike itself • 3D simulations of radiation particle strikes in DVS and sub-threshold circuits need to be performed for an accurate analysis (for example, obtain the fraction of QD that is collected) • We performed 3D simulations of a radiation strike in an inverter implemented using a 65 nm technology for different supply voltages (from nominal value to <VT)

9. Previous Work • Palau et al. 2003 studied radiation-induced transients and SER in SRAMs using a 3-D device simulation tool • Studied effects of different radiation particle tracks on SER • Effect of voltage scaling on SER not studied • Irom et al. 2002 performed an experimental study of the effects of radiation strikes in PowerPC microprocessors • Processors were implemented using 0.18 mm and 0.13 mm technologies • Reduction of core voltage from 1.6 V to 1.3 V had little effect on SER • Flament et al. 2004 experimentally evaluated the sensitivity of various commercial SRAMs to radiation strikes for different supply voltages (VDD) • SRAMs implemented using technologies ≥ 0.18 mm with VDD ≥ 1.5 V

10. Previous Work • Hazucha et al. 2000 obtained an empirical model for estimation of SER for a 0.6 mm CMOS process as a function of the critical charge and VDD through experiments and simulations • A latch with diodes was used for SER measurements for VDD ≥ 2.2V • 3D simulations of a radiation particle strike in diode were performed • The above work was conducted in older technologies • No circuit level hardening guidelines were proposed • DSM technologies and voltage scaling exhibit different behavior • Cannot be used to predict susceptibility of DSM devices at lower VDD

11. in Simulation Setup SPICE Model Radiation Particle out Set to GND Cload INV 3D Device Model • Implemented in a 65nm bulk technology • A radiation particle strike at the drain ofthe NMOS of INV • Simulated using Sentaurus-DEVICE • Mixed-level device and circuit simulator • Varied VDD from 0.35V to 1 V • To simulate sub-threshold and DVS circuits • |VT| of the PMOS transistor is 0.365V • 3 different INV sizes were simulated • 2X, 4X and 15X • LET of heavy ions considered are 2, 10 and 20 MeV-cm2/mg • To simulate low, medium and high energy particle strikes • Also simulated 4X INV with a radiation strike of LET = 2 & 10 MeV-cm2/mg (with different load capacitances) and VDD = 1V • To analyze the effect of loading on the radiation susceptibility of the INV

12. in NMOS Device Modeling SPICE Model out1 Cload INV Heavy Ion Punch through implant Halo implants VT impant 3D Device Model G Well Contact S D Constructed NMOS transistors using Sentaurus-Structure editor tool Gate length 35nm, Tox = 1.2nm spacer width = 30nm A heavy ion strikes at the center of the drain

13. NMOS Device Characterization Characterized the NMOS device using Sentaurus-DEVICE Width = 1mm Good MOSFET characteristics

14. Results and Discussions • Radiation strikes at the output of 4X INV for VDD = 1V • Low energy particle is also capable of producing significant voltage glitch • For LET = 2 the drain current looks like double exponential • Most of the charge gets collected by drift process • For larger LET values, there is a plateau • Heavily doped substrates demonstrate charge collection due to both drift and diffusion processes– in DSM processes, substrates are heavily doped

15. Results and Discussions • O1 – Small devices collect less charge compared to large devices • Reverse biased electric field is present for shorter duration in small devices • Lower drain area – less charge is collected through diffusion • G1 – If we upsize a gate to harden it, a higher value of Qcoll should be used • Extremely important for low voltage operation • O1.1 – For low energy strikes, Qcoll remains roughly constant across different gate sizes for nominal voltage operation

16. Results and Discussions • O2 – For low energy strikes, wide devices collect almost thesame amount of charge acrossdifferent VDD values • Reverse biased electric field is present for a long duration • Most of the charge gets collected within a few picoseconds after the strike • G2 – For SPICE simulations and circuit hardening against low energy strikes, it is safe to assume that Qcoll remains constant across different VDD values for wide devices • O2.1 – Qcollreduces with decreasing VDD • At lower VDD, the electric field is weaker than at higher VDD • At higher VDD, the PMOS device is stronger hence, reverse biased electric field is present for a long duration

17. Results and Discussions • O3 – The effect of radiation strikes becomes severe for VDD < 0.6V • The PMOS which is primarily responsible for recovery becomes weaker at lower VDD values • G3 – DVS should scale VDD to 2VT(~60% of nominal value) • A circuit should be hardened at the lowest operating voltage against charge collected at that voltage • Sub-threshold circuits & circuits with VDD < 2VT need aggressive protection • 4X INV, VDD = 1V varying Cload • O4.1 – For medium or high energystrikes, area of voltage glitch increases with increasing Cload • Voltage glitch magnitude roughly independent of Cload • Cload↑ => recovery time ↑ • Against common belief

18. Results and Discussions • O4.2 – For low energy strikes, increasing Cloadimproves the radiation tolerance of INV • Magnitude of the voltage glitch reduces with increasing Cload • Difference in magnitude is more for low energy strikes • PMOS has to recover a lower voltage swing • O4.3 – Qcollincreases with increasing Cload • G4 – Cload should be kept low in circuits operating in high energy radiation particle environments • Contrary to conventional wisdom • For low energy radiation environments, Cload should be kept high

19. Model for Charge Collected • Qcoll heavily depends upon VDD, LET and gate size • For SPICE level simulations and circuit hardening, worst case Qcollis usually used • May lead to pessimistic designs if this approach is used for hardening DVS circuits • Need accurate models for Qcollto improve the accuracy of SPICE simulations • We propose one such model • KMAX .LET – maximum amount of charge that can be collected. KMAX is obtained from 3D simulations at nominal VDD • The second term is obtained by curve fitting to the Qcollobtained from 3D simulations • Parameters of this model be added to SPICE model cards for MOSFETs

20. Model for Charge Collected • Curve fitting was performed for VDD = 0.6V to 1V • Applicable to circuits employing DVS • For medium and high energy particle strikes – hardening needs to be performed against such particles • KMAX = 0.8, KQ = 16.54 fC, b1 = 0.704, b2 = 0.9 and b3 = 0.664 • Avg. Error is just 6.3% • For low energy strikes, Qcoll remains almost constant • For sub-threshold circuits, it is difficult tofind an accurate model • Charge collection efficiency is very low

21. Conclusions • DVS and sub-threshold circuits are increasingly used in VLSI systems • Important to analyze the effects of radiation particle strikes in these circuits • Harden the circuits based on this analysis • Performed 3D simulations of a radiation particle strike in an INV with DVS and for sub-threshold operation • Made several observations which are important to consider during radiation hardening of these circuits • Also proposed several guidelines for radiation hardening • Proposed a model for Qcollto improve accuracy of SPICE simulations – small error of 6.3%

22. Thank You

23. Backup Slides

24. Layout Guidelines G G D S D S D G1 G2 G G S DS D S G1 G G1 G2 G 2 G G 1 G 2 d SS SS SS SS D S D S D S D S • In DSM technologies, a significant amount of charge is collected through diffusion • Depends upon the drain-substrate junction area • Reduce the drain-substrate junction area • Share output diffusion node • Not always possible • Split one big device into 2 smaller devices and connect them in parallel • Place them a certain distance (d) apart from each other • When one transistor get struck by a radiation strike, the other collects very little charge • Simulated INV of different sizes with the NMOS transistor implemented inthis manner

25. Layout Guidelines Considered vertical and angled strikes – angled towards the second transistor Vertical strike is the worst case strike for a single device Qcoll can be reduced by up to 14.5% If d is small (< 2 mm) then Qcoll is higher for angled strikes compared to vertical strikes (not shown) – use single device

26. Standard Cell Layout Guidelines VSS N Device n-well P Device VDD VDD P Device P Device 2.6 mm n-well n-well N Device N Device VSS VSS • Preference 1 – Reduce the output diffusion area by sharing if possible • Not applicable to devices connected in parallel • Preference 2– Split devices, separate them by d ≥ 4 mm and connect them in parallel • For a 65 nm n-well process • PMOS devices collect less charge compared to NMOS devices because of lower collection volume • NMOS need to be separated from each other by ≥ 4 mm • This helps reduce Qcoll by 10-14%