1 / 25

Radiation tolerance of 65 nm technology

Radiation tolerance of 65 nm technology. Sandro Bonacini CERN PH/ESE/ME sandro.bonacini@cern.ch. O utline. Test description Type of devices under test Measurement setup & conditions Total Ionizing Dose effects results Threshold voltage shift Leakage current Transconductance reduction

chelsi
Download Presentation

Radiation tolerance of 65 nm technology

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Radiation tolerance of 65 nm technology Sandro BonaciniCERN PH/ESE/ME sandro.bonacini@cern.ch

  2. Outline • Test description • Type of devices under test • Measurement setup & conditions • Total Ionizing Dose effects results • Threshold voltage shift • Leakage current • Transconductance reduction • Aggregated effects on digital structures • Single-Event Upset measurement results • SEU, MBU • Present work & future plans Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

  3. Test structures, measurement setup Ring oscillator Shift-register • One chip with digital logic • Assembled with foundry standard cells, pads and IP blocks • Packaged, functional tests & irradiation measurements run on a custom test board • Shift-register • 64 kbit • Ring oscillator • 1025 inverters • SRAM (from foundry compiler) • 56 kbit • Irradiation up to 200 Mrad X-rays while operating • One chip with devices and analog structures • Transistor devices • Irradiation & measurement at probe station, no bonding • Analog blocks • Preamplifier • Discriminator • Binary weighted DAC • Sub-binary radix DAC • Irradiation up to 200 Mrad X-rays under worst-case static bias SRAM Test devices Analog structures

  4. Parasitic MOS 2. Effects in the thick lateral isolation oxide (STI) between source and drain of a transistor Parasitic channel Field oxide Bird’s beak Source Drain 1. Effects in the thin gate oxide TID effects on CMOS technology • Threshold voltage shift • Leakage current Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

  5. Core NMOS radiation performance • Up to ~20mV shift for 200 Mrad • Some rebound effect visible for narrow devices • in 130nm: was 150mV • At high doses Vth shift is positive for wide devices, negative for narrow devices • STI edge oxide traps considerable charge (RINCE) • Subtreshold slope does not change significantly • Less than 10× increase in leakage for wide devices (W > 360nm) • Narrow devices have up to 2.5 orders of magnitude increase Threshold voltage shift Leakage current Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

  6. Core NMOS, leakage vs spread Parameter spread 1σ • Radiation-induced leakage variation is comparable to transistor parameter spread Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

  7. Core NMOS, leakage current • 65nm has better performance with respect to 130nm: (Plots are in the same scale) • a rebound effect is visible in 130 nm: • all 130nm devices are peaking at ~100nA • Narrow devices increase Ileak by 3 orders of magnitude • Ileak is ~1nA @136 Mrad 130 nm 65 nm 106 107 • TID [rad] 108 F.Faccio et al., “Radiation-induced edge effects in deep submicron CMOS transistors”, IEEE Tr. Nucl. Sci. 2005 Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

  8. I/O NMOSradiation performance • Vth shift is positive at high doses • Up to ~200mV for 200 Mrad • Vth,0 is ~500mV • Interface states seem to dominate over trapped charge • Some rebound effect visible for narrow devices • Bigger shift for narrow devices • Similar to 130nm • max 170mV @136Mrad • Increase in leakage by 2 orders of magnitude • Most around 1 Mrad, then saturates • No rebound within 200 Mrad • Enclosed Layout Transistor (ELT) structure is advised Threshold voltage shift Leakage current Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

  9. I/O NMOS, leakage current • Comparison with 130nm: (Plots are in the same scale) • devices had Ileakpeaking at 1uA @ 2Mrad • had ~5-6 orders of magnitude increase • Similarcurrent 100pA@136Mrad • 90 nm technology looks like 130nm (same foundry) 130 nm 65 nm Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

  10. Core PMOS, threshold voltage shift • PMOS Vth shift limited to 60 mV • trapped charge and interface states sum up • More evident for narrow devices • Less than 10mV for transistors with W>1um • Compared to other technologies • Better performance than 130 nm • had up to 90mV @136Mrad • 30mV for wide devices • In a 90 nm tech we observed a similar effect: 70mV @ 200Mrad Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

  11. Core PMOS, gm,maxreduction • Radiation kills maximum gm,max (strong inversion) • ...but not gm in weak inversion region • Could influence the speed of digital logic • Affects only PMOS gm,max Max. drive current Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

  12. I/O PMOS, threshold voltage shift • Considerable shift of the threshold voltage • Up to 800 mV (+160%) for 200 Mrad • Vth0 is ~550mV • More pronounced for narrow channel transistors • Devices turn off • Design must be oversized • Worse performance than in 130nm • Had max 450mV shift @136Mrad • Similar to 90 nm • Seen 600mV @200 Mrad Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

  13. I/O PMOS, gm,max reduction • Similar effect on gm,maxin strong inversion as seen for core devices • Maximum drive current is greatly reduced due to Vth and gm decrease • Necessary to oversize transistors gm,max Max. drive current Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

  14. Digital test structures: SRAM, S-R • Measured static and dynamic currents of SRAM and shift-register • Dynamic test run @ 30MHz • SRAM static current increases by 300× • Dynamic current reflects this change with a small increase • Ultra-narrow devices are used in the SRAM from foundry (W=80nm) • Peak current at ~2-3 Mrad • Dependent on dose rate (?) • Shift-register static current changes very little • Dynamic current practically constant (decrease!) • ~12.5 nW/MHz per D-FF • Visible partial annealing effect at room temperature • Time constant ~ 1.5 hours annealing100 °C, 1 week 13.8 hours annealing • 25 °C annealing 25 °C Dose [×100 Mrad] Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

  15. Digital test structures: ring-oscillator • Ring oscillator • Logic slows down with radiation • -13.8% • Must keep margin in digital design • …or select cells with wider transistors • Due to PMOS drive current reduction • Current and speed remain proportional • ~ 3 nW/MHz for 1 inverter • Annealing 100 °C, 1 week Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

  16. SEU test results, tech. comparison • 65nm seems to saturate at a cross-section 3.4× smaller than 130nm • About proportional to 4× area reduction • 90nm registers were custom-made (not standard cells) • Higher saturation cross-section though area is ½ of cell in 130 nm • LET thresholds are less than 1.1 MeVcm2/mg for all technologies • Note: SEU-robust cells are well below 10-10 cm2/bit Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

  17. Multiple Bit Upsets (MBUs) in SRAM • Plots above are @1.2V supply • Most MBUs occur in adjacent cells along n-wells (SRAM cell is ~1.0x0.5um) • (...along bit-lines and not along word lines, due to internal SRAM structure) • Lower power supply worsens MBU contribution (up to 7-BU @0.9V, 0 deg) • Shift-register MBUs are <1% (2-BU and 3-BU were seen) LET = 20.4 MeVcm2/mg (Ar, 60 deg tilt) Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

  18. MPW 26 November 2012 • Test chip with several ring oscillators made of library inverters of different size • … to test the impact of TID on the speed of logic gates • DICE cell SEU test chip • Demonstrators: • Low-power SEU-robust serializer 4.8 Gb/s • CLICpix, imager with 25um pixel size Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

  19. Thank you… 65 nm demonstrates a better radiation hardness than previous generation technologies No ELT for digital logic …but wide PMOSes help limiting drive/speed loss I/O devices still need ELT PMOS might need to be oversized SEU performance is better as sensitive areas are smaller But beware in using more logic in chips More evident MBUs Additional information can be found in “Mechanisms of Noise Degradation in Low Power 65 nm CMOS Transistors Exposed to Ionizing Radiation”, V.Re, L.Gaioni, M.Manghisoni, L.Ratti, G.Traversi, IEEE Tr. Nucl. Sci., Vol.57, No.6, Dec. 2010 Future plans Design CMOS I/O standard pad library Select cells in standard cell library from foundry with devices WPMOS> 500nm (TBD) MPW in Nov. 2012 TID std. cell test structures, DICE SEU test, ClicPix, Low-power GBT Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

  20. Thank You Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

  21. SEU test results – heavy ion beam • No substantial differences between static test and dynamic test run at 30 MHz • Evidence of 1 clock root SEU hit • SRAM cell is 13× smaller than DFF • Max 1.7× increase in cross-section with reduced power supply voltage @ 0.9V Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

  22. PDK, metal stack and libraries passivation RDL RDL M6 M6 M5 M5 M5 M4 M4 M4 M3 M3 M3 M3 • Many tech. options but they all come at a cost • Thin metals are expensive because of their fine pitch M2 M2 M2 M2 M1 M1 M1 M1 M1 M1 W W W W W poly poly STI • Integrate OA PDK and library to form a M/S kit • One metal stack and one library delivered at first • 4 thin + 2 thick • no mimcaps included by default • tcbn65lp • Available later (TBD): • Second option of metal stack • 3 thin + 2 thick • Second option for library • tcbn65lpbwp7thvt

  23. Rad-hard CMOS I/O pad library • Standard I/O pad library from foundry suffers from radiation effects • Use of 2.5V-rated transistors with >5-nm-thick gate oxide • NMOS leakage • PMOS tend to turn off + loss in transconductance • ~50% loss in maximum drive current within 200 Mrad • Speed reduction • Radiation hardened I/O pad library • Rated for 1.2 V • Only core devices, thin gate oxide • Better radiation performance • To be packaged together with the OA M/S design kit

  24. Motivation • Future vertex detectors for high energy physics experiments can benefit from modern deep submicron technologies • Scaling is necessary to improve the performances of pixel detectors • Smaller pixel sizes (pitch) • More “intelligence” in each pixel • Faster serializers • In general, the expected advantages in porting a front-end circuit to a more advanced technology include • A much more compact, faster digital part (reduction in area of ~60% compared to 130nm technology) • Lower noise equivalent charge, due to the reduced capacitances associated with smaller pixels • Better matching than in 130nm • Studies on radiation hardness of the selected technology are needed • A set of test chips was designed, fabricated and tested to assess radiation hardness and functionality of both analog and digital test structures Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

  25. Drawbacks of 65 nm Higher cost of tape-out compared to older technologies Strong push for 1st working silicon Push for more IP re-usage? Must limit technology options usage Higher gate leakage current More stringent design rules: ELT transistors are not allowed, more difficult to achieve an optimal layout. OPC rules: avoid jogs, zigzag, shapes like “L”, “U” or ring, … Deep submicron technologies are not optimized for analog designs Smaller dynamic range due to the lower power supply (1.2 V) reduces the possibilities to use some structures (such as cascoded stages). Multiple stages, with possible stability issues, are needed to achieve a high gain. This problem is moreover aggravated by the lower output resistance of the MOSFETs which lowers the gain of the single stages. Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

More Related