Results of the TLK1711-A Radiation Tolerance Tests

1. Results of the TLK1711-A Radiation Tolerance Tests A. Aloisio, R. Giordano Physics Dept. - University of Napoli “Federico II” and INFN Sezione di Napoli, Italy email: aloisio@na.infn.it, rgiordano@na.infn.it

2. Outline • On-detector SerDes in the ETD framework • TLK2711-A: serial protocol & parallel IO • Test-bench for TLK2711-A • Test facility and conditions • Results • Conclusions Raffaele Giordano SuperB Workshop, Frascati Apr. 2011

3. SerDes in rad enviroments Layout by D. Breton LNF, Dec.09 • FCTS links: • Timing & Clock • Commands & Controls • config data • DATA links: • No tight latency requirements • 2.5 Gbps • Read-out payload • TLK2711-A is a candidate SerDes B-Type Links C-Type Links FCTS link Tight latency requirements DS92lv18 Data link No tight latency requirements DS92lv18 or TLK2711A Raffaele Giordano SuperB Workshop, Frascati Apr. 2011

4. Serial Protocol & Parallel IO • Data rate: 1.6 to 2.7 Gbps • Clock range: 80 to 135 MHz => experiment clock needs to be multiplied externally (56 x 2 MHz), more components, more jitter injected in stream • 8b10b encoding with 18-bit input bus: 16 bit payload+ 2 K control bits (KMSB & KLSB) • 20-bit encoded words • Latency variations up to 4 UIs on Tx and 31 UIs on Rx Raffaele Giordano SuperB Workshop, Frascati Apr. 2011

5. Alignment Mechanisms • Deserializer aligns on specific 8b10b symbol pair (K28.5 on LSB + D5.6 on MSB) • Deserializer recognizes only ‘0011111’ comma (not the inverted version) and aligns it to the LSB • Two dedicated pins (RKLSB and RKMSB) flag if the data (on LSB or MSB) is an 8b10b K-character • No lock flag, external logic needed to decide if lock has been achieved by monitoring RKLSB flag and data from the SerDes Raffaele Giordano SuperB Workshop, Frascati Apr. 2011

6. TLK Symbol Error Tolerance • Single or ‘short’ error bursts do not imply loss of lock (recovered clock) • TLK tolerates hundreds of «not in table» 8b10b symbols before unlocking PLL phase from stream • Even then, the device still provides an output clock, which is derived from the local input clock not from the stream Raffaele Giordano SuperB Workshop, Frascati Apr. 2011

7. TLK2711-A Test board Diff. impedance 120 W • High speed I/O and clocks on SMA connectors with controlled impedance • RX, TX, Controls busses on parallel connectors with matched length and controlled impedance • Static control programming enabled via jumpers • Separate supplies for analog (analog Tx,Rx and PLL), digital (core+IO) sections with sense (4-wire scheme) • Current sensing on each supply • 10 layer PCB, separate power and ground planes TX out TX clk RX in Recovered Clock 57 W Raffaele Giordano SuperB Workshop, Frascati Apr. 2011

8. An X-Ray View of the TLK2711-A • 64 pin plastic package, size: 12x12 mm2 • Die size: 1.9x1.9 mm2 7.5 mm 0.5 mm 0.23 mm 1.88 mm Die All linear units are mm. Raffaele Giordano SuperB Workshop, Frascati Apr. 2011

9. Tektronix DTG5334 18 2 8 18 Controls RX Data out TLK2711A Test Bench Ethernet link Ethernet link BRIDGE RS-232 link XILINX ML505 PC logging all the data on the hard-drive (errors, static and dynamic currents…) Recovered Clk Clock Generator FPGA Clk TX Clk TX Data in Ethernet link Power Analyzer & Logger Controls RX Serdes TX Serdes 2.5V Power AGILENT N6705A Raffaele Giordano SuperB Workshop, Frascati Apr. 2011

10. FPGA setup Console I/O Parallel I/O Clock output • Data pattern stored in the FPGA firmware • Testing the SerDes RX section • Drives the SerDes receiver input with 8b10b serial stream • Receives SerDes parallel output • Cross check received data vs. transmitted • Logs errors • Testing the SerDes TX section • Drives the SerDes transmitter input with parallel data • Receives the SerDes serial stream • Cross check received data vs. transmitted • Logs errors • Controls section • Programs controls bits • Console • Status and errors are logged on a console handle by an embedded micro XILINX ML505 Virtex5 – XC5VLX50T Clock input GTPdiff. I/O • TX and RX sections of the SerDes are tested independently and simultaneosly Raffaele Giordano SuperB Workshop, Frascati Apr. 2011

11. Test Time Slicing: BER View Log file • Test time unit of 10 s • Each unit consists of 2 time slices: • Data error logging and “dynamic” currents measurement ~ 9.5 seconds • “Static” currents measurement (powerdown) ~ 500 ms Time Unit N-1 Time Unit N Time Unit N+1 Raffaele Giordano SuperB Meeting, Frascati Apr. 2011

12. Test Time Slicing: Current View Log of the current drawn by the digital power • Both dynamic and static currents are measured during each time unit Dynamic current Measurement (during Bit Error Ratio Test) Current (A) one time unit (10 s) Static current measurement Time (s) Raffaele Giordano SuperB Workshop, Frascati Apr. 2011

13. Data Error Log • Monitor Errors in the payload (either single or burst) • Each data error is time-stamped with clock period resolution • Expected vs and wrong word => we know exactly which bit(s) flipped Time Stamp Relative to TU Error on Tx Time Stamp Corrupted 00101000011000111 Expected 00101011011000111 Double Bit Error Raffaele Giordano SuperB Workshop, Frascati Apr. 2011

14. LNS Facility Experimental setup LNS accelerator PLAN • Superconductingcyclotronat LNS - Catania • 62-MeV protonbeam • CATANA beam line • Currenttunable up to 300 pA • Uniformbeamintensity on our sample • Wetested 3 TLK2711A chips Beam spot 25 mm 2D Beam profile Raffaele Giordano SuperB Workshop, Frascati Apr. 2011

15. Sample no. 1: Beam Facts beam spot • During this test • Ibeam ~ 300 pA • Time on beam = 20 min • Total dose in Si ~ 760 Gy • Dose rate = 36 Gy/min (Si) • Total Nprotons ~ 1.18·1010 (on die) • Vcc = 2.5 V (typical condition) • fclock = 100 MHz • Data rate during test=2 Gb/s Front view TLK2711-A Test-board Wider Front view Parallel & Serial Data cables FPGA board Raffaele Giordano SuperB Workshop, Frascati Apr. 2011

16. Sample no. 1: Error Results • 3 single Txerrors • First erroroccurredafterat a dose of ~ 420 Gy (Si) • At a dose ~ 700 Gy (Si): • BothTx and Rxstoppedworking, functionalfailure (i.e. >1000 errors per TU) • Tx: incorrect data pattern from the verybeginning of each TU • Rx: data pattern correct for ~ 1-2 s, thencontinuoserrors stx= 9.2 10-12 cm2 Raffaele Giordano SuperB Workshop, Frascati Apr. 2011

17. Sample no. 1: Digital Current Trend • Digital dynamiccurrentincrease from 153 mA to 200 mA • Severe power down currentincrement from 3.8 to 55 mA, more than 10 times! Static Dynamic Functional failure Raffaele Giordano SuperB Workshop, Frascati Apr. 2011

18. Sample no. 1: Analog Current Trend • Moderate dynamic current increase from 53 mA to 55 mA • Power down current increment from 1.6 to 4.2 mA, more than 300% Static Dynamic Chip failure Raffaele Giordano SuperB Workshop, Frascati Apr. 2011

19. Sample no. 2: Beam Facts • Decided to irradiate the sample more slowly, in order to better observe current trends and tx/rx errors • During this test • Ibeam ~85 pA (less than 1/3 of sample no.1) • Time on beam = 103 min (5 times the time of sample no. 1) • Total dose in Si ~ 1060 Gy • Dose rate = 10 Gy/min (Si) • Total Nprotons ~1.6·1010(on die) • Vcc = 2.5 V (typical condition) • fclock = 100 MHz • Data rate = 2 Gb/s beam spot Front view TLK2711-A Test-board Wider Front view Parallel & Serial Data cables FPGA board Raffaele Giordano SuperB Workshop, Frascati Apr. 2011

20. Sample no. 2 : Error Results • First error appeared at dose = 280 Gy (Si) • # Tx errors = 2 single and 1 burst (7 consecutive errored symbols) • # Rx errors = 0 single and 2 burst (12,11 consecutive symbols) • At dose = 800 Gy (Si), the device underwent functional failure stx(single)=4.3 10-12 cm2 stx(burst)=2.1 10-12 cm2 srx(burst)= 4.3 10-12 cm2 Raffaele Giordano SuperB Workshop, Frascati Apr. 2011

21. Sample no. 2: Current Trends Digital • Same trend as sample no. 1, better resolved thank to slower irradiation • Chip failure at dose= 800 Gy (Si) Dynamic Static Analog Dynamic Static Raffaele Giordano SuperB Workshop, Frascati Apr. 2011

22. Sample no. 2: Annealing Digital • Annealing: keptdeviceworkingat room temperature afterirradiation (~ 2 hours) • Functionalityrestored in ~ 10 minutes • Currentwouldprobablyneeddays to go back atinitialvalues Dynamic Static Analog Dynamic Static Raffaele Giordano SuperB Workshop, Frascati Apr. 2011

23. A Very Sensitive Device • Beforeirradiationwemonitored the currentsincebefore and afterplacing the deviceclose to the collimator (~ 10 cm) for irradiation • The collimatorhasbeenactivated by the beamused for sample no. 1 • Dynamicdigitalcurrentincreased from 157.3 mA to 157.5 mA Device ‘close’ to the collimatior Device ‘far’ from to the collimatior Raffaele Giordano SuperB Workshop, Frascati Apr. 2011

24. Sample no. 3 • Decided to irradiate the sample even more slowly than sample no. 2 • During this test • Ibeam ~40 pA (1/2 of sample no.2) • Time on beam = 176 min • Total dose in Si ~ 762 Gy • Dose rate = 4 Gy/min (Si) • Total Nprotons ~1.19·1010(on die) • Vcc = 2.5 V (typical condition) • fclock = 100 MHz • Data rate = 2 Gb/s Raffaele Giordano SuperB Workshop, Frascati Apr. 2011

25. Sample no. 3 : Summary of Results • Currentsexhibitedverysimilar trends to those of sample no. 2, bothduringirradiation and annealing • First errorappearedat dose = 280 Gy (Si) • # Txerrors = 1 single and 2 burst (4,3 consecutive erroredsymbols) • # Rxerrors = 2 single and 2 burst (4,3 consecutive symbols) • At dose = 760 Gy (Si), the deviceunderwentfunctionalfailure stx(single)=3.0 10-12 cm2 stx(burst) = 6.1 10-12 cm2 srx(burst) = 6.1 10-12 cm2 stx(burst) = 3.0 10-12 cm2 Raffaele Giordano SuperB Workshop, Frascati Apr. 2011

26. A Few Remarks • Device is easier to use than DS (‘felt’ during test design) • No loss-of-lock problem to be managed • Standard coding, easier to implement with standard FPGA-embedded SerDeses • Radiation issues • Had to leave tested and control boards in hot room • All cabling (power, serial, parallel) is now activated and has to be replaced Raffaele Giordano SuperB Workshop, Frascati Apr. 2011

27. We monitored currents (static and dynamic for the analog and digital sections) and data errors as function of time (and therefore absorbed dose) for 3 TLK2711A devices We found both single and burst (i.e. consecutive) word errors We observed bursts long up to ~ 10 words Muchhighersensitivity to radiationthanDS92LV18 Dynamic and staticcurrentsexhibitedwellrecognizable trends Chip Failure (bothTx and Rxat ~ 600 Gy (Si)) Need a radiation map to decide whether or not the device can be used in the ETD Wewish to thank Giacomo Cuttone, G. A. P. Cirrone, Francesco Romano and all the LNS staff for its help and supportduringourtest beam Conclusions Raffaele Giordano SuperB Workshop, Frascati Apr. 2011

28. Back-up Slides Raffaele Giordano SuperB Workshop, Frascati Apr. 2011

29. Quick Facts • rSi = 2.3 g/cm3 • (dE/dx)proton at 60MeV in Si = 1.8 MeV/mm (or 600 keV in 300 mm) • s = (1 / F) * nerrors Raffaele Giordano SuperB Workshop, Frascati Apr. 2011