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Logic Design

Logic Design. Content (1/2). Boolean Functions 3 lectures Boolean Functions Minimization. Combinational Logic Design Principles 4 lectures Brief Description of Verilog 3 lectures Basic Combinational Circuits 4 lectures Finite States Machines (FSM) 3 lectures

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Logic Design

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  1. Logic Design

  2. Content (1/2) • Boolean Functions • 3 lectures • Boolean Functions Minimization. Combinational Logic Design • Principles • 4 lectures • Brief Description of Verilog • 3 lectures • Basic Combinational Circuits • 4 lectures • Finite States Machines (FSM) • 3 lectures • Synthesis of Synchronous FSM • 5 lectures

  3. Content (2/2) • Basic Sequential Circuits • 3 lectures • Problems of Synchronous Design • 3 lectures • Asynchronous FSM. Self-Timed Circuits • 3 lectures • Arithmetic Units • 4 lectures • Programmable Logical Integrated Circuits (PLDs) • 3 lectures • Memory Devices • 3 lectures

  4. CLK TH TL flip-flop outputs TCLK TFFPD TCOMB TSETUP THOLD Setup time margin Timing Diagram TFFPD- some time between the rising edge of CLK and change flip-flop outputs (Tclk-to-q)

  5. Timing Parameters tcomb - time, required for the flip-flop changes to propagate through combinational logic elements (flip-flop) excitation logic. The condition for proper circuit operation: TCLK – TFFPD – TCOMB > TSETUP Setup-time margin TCLK – TFFPD(max) – TCOMB(max) - TSETUP >=0 Hold-time margin TFFPD(min) + TCOMB(min) – THOLD >=0 Critical path delay – propagation delay through the longest path.

  6. IN Clock Q1 tskew Clock D incorrect Q2 Clock Skew Clock skew – a difference between arrival times of the clock at different devices. Q2 Q1 IN D D Q FF1 FF2 Clock correct

  7. Critical path – 4 logic levels Clock Cycle Time – Critical Path Delay Cycle time(T)cannot be smaller than longest path delay (Tmax) Tmax + Tsetup + Tskew +T clk-to-Q T T Data

  8. D D D D D A Clock-signal Path Leading to Skew Clock

  9. Clock D D D D D D Clock Signal Routing to Minimize Skew(Clock Tree)

  10. Syncin D C Asyncin Synchronous system Clock Asynchronous Inputs Digital systems of all types unavoidably must deal with asynchronous input signals that are not synchronized with the system clock. A single simple synchronizer

  11. Clock Asyncin SYNCIN A single simple synchronizer If an input signal is missed at one clock tick, it can always be detected at the next one.

  12. SYNC1 Synchronous System D Asyncin SYNC2 D Clock Two Synchronizers for the Same Asynchronous Input Two flip-flops will not see the clock and input signals at precisely the same time. When asynchronous input transitions occur near the clock edge, there is a small window of time during which one flip-flop may sample the input as 1, and the other – as 0.

  13. Synchronizer Failure and Metastability • There are two ways to get a flip-flop out of the metastable state: • Use the faster flip-flops with short setup time • Wait ”long enough”, so the flip-flop comes out of metastability on its own • Metastability resolution time Тr • Tr=Tclk –Tcomb–Tsetup • In order to maximize Тr for a given clock period we should minimize Tcomb and Tsetup.

  14. Q1 D C Asyncin Synchronous System Clock D C Q2 Example of Synchronizer

  15. META Synchronous System ASYNCIN SYNCIN D Q D Q FF1 FF2 CLOCK Reliable Synchronizer Design Tcomb=0 If the clock period is greater than Tr+Tsetup FF2 SYNCIN becomes a synchronized copy of the asynchronous input ASYNCIN on the next clock tick without ever becoming metastable itself.

  16. Clock Tclk D stable stable Ts Th Decision window Q Tpd Timing Parameters for Metastability Analysis unstable Ts Th Decision window Metastable Tr Normal flip-flop operation Metastable behavior

  17. Deskewed SyncIN AsynchIN Meta SyncIN Synchronous System D C D C D C Divide-by-N counter Clock Multiple-Cycle Synchronizer with Deskewing

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