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Low Power Device Issues Peter M. Zeitzoff Panel Discussion

Low Power Device Issues Peter M. Zeitzoff Panel Discussion. Transistor intrinsic delay, t t ~ C V dd /(I on *W) I on units: µA/µm C = C s/d + C L Gate dominated (local, dense logic) C ~ C gate ~ C ox *W*L g + C parasitic C ox ~ e ox /T ox

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Low Power Device Issues Peter M. Zeitzoff Panel Discussion

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  1. Low Power Device IssuesPeter M. ZeitzoffPanel Discussion

  2. Transistor intrinsic delay, t t ~ C Vdd/(Ion*W) Ion units: µA/µm C = Cs/d + CL Gate dominated (local, dense logic) C ~ Cgate ~ Cox*W*Lg + Cparasitic Cox ~ eox/Tox Transistor intrinsic switching frequency = 1/ t: key performance metric To maximize 1/t,maximize Ion Impact of Key MOSFET Parameters on Circuit Performance

  3. High performance logic (MPU, for example) Driver: maximize chip speedmaximize transistor performance Goal of ITRS scaling: 1/t increases at ~ 17% per year, historical rate Must maximize Ion Consequently, Ileak is relatively high Low power logic (mobile applications) Driver: minimize chip powerminimize Ileak Goal of ITRS scaling: specific, low level of Ileak Consequently, 1/t is relatively reduced Lg, Tox, etc., are scaled more slowly than for high-performance logic ITRS Drivers for Different Applications

  4. Isd,leak, High Perf. 1/t , High Perf. (target) 1/t, Low Power Isd,leak, Low Power (target) Scaling of Leakage Current and 1/t

  5. Simulated Jg, oxynitride Specified Jg (<Isd,leak/Lg per 2001 ITRS) 1.E+02 3 1.E+01 EOT 2.5 1.E+00 1.E-01 2 ) Beyond this point, oxynitride too leaky; high K needed 2 1.E-02 (A/cm EOT (nm) 1.5 1.E-03 g J 1.E-04 1 1.E-05 LSTP is projected to drive the implementation of high-k gate dielectric in ~2005. 0.5 1.E-06 1.E-07 0 2001 2003 2005 2007 2009 2011 2013 2015 Year LSTP: Maximum Gate Leakage Spec’s. and Simulations: Need for High K

  6. Vdd-Low Power Vdd-High Perf. Vt-Low Power Vt-High Perf. Vdd and Vt Scaling

  7. Scaling of low-power logic transistors is driven by meeting low leakage current specifications Vdd is scaled very slowlydifficult scaling of Tox and Lg Lg, Tox scaled more slowly than for high-performance logic High-k gate dielectric required by ~2005 There is a performance trade-off because of the low leakage current Summary

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