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Computer Architecture

Computer Architecture. Lecture 5: Addressing modes Piotr Bilski. Why do we need different addressing modes?. Real or virtual memory space is larger than space referred to by the argument (too small number of bits)

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Computer Architecture

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  1. Computer Architecture Lecture 5: Addressing modes Piotr Bilski

  2. Why do we need different addressing modes? • Real or virtual memory space is larger than space referred to by the argument (too small number of bits) • A compromise between the address range and simplicity of the address fetching is needed

  3. Real (effective) and virtual address • The real address is the address of the physical location in the memory • Virtual address (effective address - EA) is the address treated as the instruction argument • Translation of the virtual address into the real one depends on the organization of the memory

  4. Symbols used • EA – effective address • R – content of the address field in the instruction referring to the registers • A – content of the addresss field in the instruction • (X) – content of the location X

  5. Addressing modes • Immediate • Direct • Indirect • Register • Register indirect • Displacement (indexed) • Stack

  6. Immediate mode 0 3 4 15 Operation code Argument value The argument is stored in the instruction using Two’s complements format. Therefore, this number can not be too large.

  7. Direct mode 0 3 4 15 Operation code Argument address memory Argument EA = A

  8. Indirect mode 0 3 4 15 Address storing information about the address of the argument Operation code memory EA = (A) Nesting possible! Argument

  9. Register mode 0 3 4 15 Operation code Name (register number) registers Argument EA = R

  10. Register indirect mode 0 3 4 15 Operation code Name (register number) registers memory Address Argument EA = (R)

  11. Displacement mode 0 3 4 15 Argument address Name (register number) Operation code registers memory Address Argument EA = (A)

  12. Displacement mode (cont.) • Relative addressing (R=PC) • Addressing with the base register (efficient for the segmented memory) – EA=R+A • Indexing (different interpretation of the register and address field that when using base register) – EA=A+R

  13. Displacement addressing (cont.) • Addressing with the base register • Indexing (uses dedicated indexing register) 0 3 4 15 Register with argument address Displacement value Operation code 0 3 4 15 Operation code Argument address Register with displacement

  14. Stack mode 0 3 4 15 Argument address Operation code stack registers Stack register

  15. Address types • Physical – location of the address in the memory • Logical – location of the address in relation to the program entry point • Base – entry point address

  16. Memory organization from the operating system level • Paged memory (model invisible for the programmer) – memory is divided into small fragments (page frames), assigned to the fragments of the programs • Segmented memory (model available for the programmer) – assures separate addressing space for every process

  17. Partitioning with the predefined size • Division of the memory into fragments of the predefined sizes (constant or varying) 16 MB (OS) 16 MB 16 MB 16 MB 16 MB (OS) 4 MB 8 MB 8 MB 16 MB

  18. Partitioning with the dynamic size • Division of the memory into fragments of the sizes depending on the processes requirements 16 MB (OS) 48 MB free 16 MB (OS) Process 1 (20 MB) 28 MB free 16 MB (OS) Process 1 (20 MB) Process 2 (16) MB 12 MB free 16 MB (OS) Process 3 (18 MB) Process 2 (16) MB 12 MB free

  19. Paging memory Process A: Page 0 Page 1 Page 2 memory 11 12 13 14 15 16 17 18 11 12 13 14 15 16 17 18 Page 0 Page 1 Page table of the process A: 11 12 15 Free frames: 11 12 15 16 18 Page 2

  20. Physical and logical addresses in the paging structure memory Physical address Logical address 11 12 13 14 15 16 17 18 Page 0 12 30 1 30 Page 1 Page table of the process A: 11 12 15 Page 2

  21. Translation Lookaside Buffer • Cache memory for the recent memory addresses translations • Very fast, but small size • TLB cooperates with the „real” cache memory • Bad design can lead to the system’s malfunctions (see Phenom processors)!

  22. Translation Lookaside Buffer (TLB) START YES Entry in TLB? Checking TLB Actualize TLB NO Access to the page table Physical address generation NO Page fault handling Page in memory? YES STOP

  23. Segmentation • Easy management of the data structures of varying size • Ability to grant individual rights of the processes to the subsequent segments • Ability to use the segment by multiple processes • Addressing: segment number + relative address

  24. Pentium address spaces • Non-segmented, non-paged memory (virtual address = physical address - drivers) • Non-segmented, paged memory (BSD) • Segmented, non-paged memory • Segmented, paged memory (UNIX System V)

  25. Pentium II Segmentation • 2 bits of the segment pointer are used for the protection mechanism • Relative address allows addressing 232 = 4 GB of memory • The overall amount of addressable memory is 216 x 232 = 64 TB • Access of the process to the segment depends on the accessibility level (indicated by the number from 0 – the highest to 3 – the lowest) Virtual address Segment pointer Relative address 16 bits 32 bits

  26. Segment Selector and Descriptor 16 3 2 1 0 Index TI PRV 0 31 D/B AVL GS 19-16 Base 31-24 G Base 23-16 P DPL S Type Base 15-0 Segment border 15-0

  27. Pentium II Paging • The page directory contains 1024 entries, which divide the memory into 1024 pages groups • Each pages group contains up to 1024 entries • Every page has size of 4 kB or 4MB (depending on the PSE bit) • Page tables can be contained in the virtual memory • Translation Lookaside Buffer contains up to 32 entries of the page tables for the particular page directory

  28. Paging/Segmentation in Pentium II

  29. Pentium addressing modes • Pentium has six segment registers (SR) to hold addresses of the first segments • Segment descriptor register is related to the segment register (contains segment access rights and its length) • Additional registers (base and index) help to assemble address

  30. Pentium addressing modes (cont.) • Immediate (Arg = A) • Register (AL = R) • Displacement (AL = (SR) + A) • Base register (AL = (SR) + (B)) • Base register with displacement (AL = (SR) + (B) + A) • Scaled index with displacement (AL = (SR) + (I) x S + A) • Base register with index and displacement (AL = (SR) + (B) + (I) + A) • Base register with scaled index and displacement (AL = (SR) + (I) x S + (B) + A) • Relative (AL = (PC) + A)

  31. Illustration of the Pentium addressing modes Segment register Indexing register Base register Selector Memory Segment base address Scale Displacement Linear address Descriptor register Border

  32. PowerPC memory management • RISC architecture – simple addressing modes! • Implementation depends on the architecture (32 or 64 bit) • Block address translation mechanism is used as the alternative to the paging mechanism

  33. Effective and real address of PowerPC • Effective address • Real address 0 3 4 19 20 31 Segment Page Byte selector 0 19 20 31 Real page number Byte alignment

  34. PowerPC addressing modes • Load/store architecture (also with update) • Indirect (AE = (BR) + D ) • Indexed indirect (AE = (BR) +(IR)) • Branch address • Absolute (AE = I) • Relative (AE = (PC) +I) • Indirect (AE = (L/CR)) • Arithmetic • Register fixed position (AE = GPR) • Immediate (Arg = I) • Register floating position (AE = FPR)

  35. Instruction format • Instruction length is limited by the breadth of the applied buses • Instruction length should be equal to the breadth of the bus or its multiplicity • A compromise between the bit number required for the instruction code and address space • Instructions containing codes of varying length are more flexible

  36. Instruction Design Criteria • Number of addressing modes • Number of operands • Number of registers and their sets • Address range • Address granularity level (byte or word addressing?)

  37. Format example: PDP-8 • Instructions and data 12 bit long • One register – accumulator • Memory is divided into the pages 27 = 128 words long • The eight bit is a pointer to the page number

  38. PDP-8 instructions Memory related instructions Input/output instructions Microoperations and register related instructions 0 2 3 4 5 11 Operation D/I Z/C Displacement 0 2 3 8 9 11 1 1 0 Device Operation code 0 3 4 5 6 7 8 9 10 11 1 1 1 x CLA CLL CMA CML RAR RAL BSW IAC

  39. PDP-10 instructions • Instruction elements are orthogonal • Only direct addressing • 36-bit instruction and data 0 8 9 12 13 14 17 18 35 Operation Register I Index register Memory address

  40. Pentium instruction format 0-4 B 1-2 B 0-1 B 0-1 B 0-4 B 0-4 B Prefixes Oper. code ModR/M SIB Displacement Immediate Address specifier

  41. PowerPC instruction format 6 b 5 b 5 b 16 b Operation Options/desti- Options/source nation register register All instructions are 32-bit long!

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