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361 Computer Architecture Lecture 8: Designing a Single Cycle Datapath

361 Computer Architecture Lecture 8: Designing a Single Cycle Datapath. Outline of Today’s Lecture. Introduction Where are we with respect to the BIG picture? Questions and Administrative Matters The Steps of Designing a Processor Datapath and timing for Reg-Reg Operations

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361 Computer Architecture Lecture 8: Designing a Single Cycle Datapath

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  1. 361Computer Architecture Lecture 8: Designing a Single Cycle Datapath

  2. Outline of Today’s Lecture • Introduction • Where are we with respect to the BIG picture? • Questions and Administrative Matters • The Steps of Designing a Processor • Datapath and timing for Reg-Reg Operations • Datapath for Logical Operations with Immediate • Datapath for Load and Store Operations • Datapath for Branch and Jump Operations

  3. Processor Input Control Memory Datapath Output The Big Picture: Where are We Now? • The Five Classic Components of a Computer • Today’s Topic: Design a Single Cycle Processor machine design Arithmetic technology inst. set design

  4. CPI Inst. Count Cycle Time The Big Picture: The Performance Perspective • Performance of a machine is determined by: • Instruction count • Clock cycle time • Clock cycles per instruction • Processor design (datapath and control) will determine: • Clock cycle time • Clock cycles per instruction • Today: • Single cycle processor: • Advantage: One clock cycle per instruction • Disadvantage: long cycle time

  5. How to Design a Processor: step-by-step • 1. Analyze instruction set => datapath requirements • the meaning of each instruction is given by the register transfers • datapath must include storage element for ISA registers • possibly more • datapath must support each register transfer • 2. Select set of datapath components and establish clocking methodology • 3. Assemble datapath meeting the requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. • 5. Assemble the control logic

  6. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 31 26 21 16 0 immediate op rs rt 6 bits 5 bits 5 bits 16 bits 31 26 0 op target address 6 bits 26 bits The MIPS Instruction Formats • All MIPS instructions are 32 bits long. The three instruction formats: • R-type • I-type • J-type • The different fields are: • op: operation of the instruction • rs, rt, rd: the source and destination register specifiers • shamt: shift amount • funct: selects the variant of the operation in the “op” field • address / immediate: address offset or immediate value • target address: target address of the jump instruction

  7. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits Step 1a: The MIPS-lite Subset for today • ADD and SUB • addU rd, rs, rt • subU rd, rs, rt • OR Immediate: • ori rt, rs, imm16 • LOAD and STORE Word • lw rt, rs, imm16 • sw rt, rs, imm16 • BRANCH: • beq rs, rt, imm16

  8. Logical Register Transfers • RTL gives the meaning of the instructions • All start by fetching the instruction op | rs | rt | rd | shamt | funct = MEM[ PC ] op | rs | rt | Imm16 = MEM[ PC ] inst Register Transfers ADDU R[rd] <– R[rs] + R[rt]; PC <– PC + 4 SUBU R[rd] <– R[rs] – R[rt]; PC <– PC + 4 ORi R[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4 STORE MEM[ R[rs] + sign_ext(Imm16) ] <– R[rt]; PC <– PC + 4 BEQ if ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4

  9. Step 1: Requirements of the Instruction Set • Memory • instruction & data • Registers (32 x 32) • read RS • read RT • Write RT or RD • PC • Extender • Add and Sub register or extended immediate • Add 4 or extended immediate to PC

  10. Step 2: Components of the Datapath • Combinational Elements • Storage Elements • Clocking methodology

  11. Combinational Logic Elements (Basic Building Blocks) CarryIn A 32 • Adder • MUX • ALU Sum Adder 32 B Carry 32 Select A 32 Y MUX 32 B 32 OP A 32 Result ALU 32 B 32

  12. Storage Element: Register (Basic Building Block) Write Enable • Register • Similar to the D Flip Flop except • N-bit input and output • Write Enable input • Write Enable: • negated (0): Data Out will not change • asserted (1): Data Out will become Data In Data In Data Out N N Clk

  13. Storage Element: Register File RW RA RB Write Enable 5 5 5 • Register File consists of 32 registers: • Two 32-bit output busses: busA and busB • One 32-bit input bus: busW • Register is selected by: • RA (number) selects the register to put on busA (data) • RB (number) selects the register to put on busB (data) • RW (number) selects the register to be writtenvia busW (data) when Write Enable is 1 • Clock input (CLK) • The CLK input is a factor ONLY during write operation • During read operation, behaves as a combinational logic block: • RA or RB valid => busA or busB valid after “access time.” busA busW 32 32 32-bit Registers 32 busB Clk 32

  14. Storage Element: Idealized Memory Write Enable Address • Memory (idealized) • One input bus: Data In • One output bus: Data Out • Memory word is selected by: • Address selects the word to put on Data Out • Write Enable = 1: address selects the memoryword to be written via the Data In bus • Clock input (CLK) • The CLK input is a factor ONLY during write operation • During read operation, behaves as a combinational logic block: • Address valid => Data Out valid after “access time.” Data In DataOut 32 32 Clk

  15. . . . . . . . . . . . . Clocking Methodology Clk Setup Hold Setup Hold • All storage elements are clocked by the same clock edge • Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew Don’t Care

  16. Step 3 • Register Transfer Requirements–> Datapath Assembly • Instruction Fetch • Read Operands and Execute Operation

  17. PC Clk Next Address Logic Address Instruction Memory 3a: Overview of the Instruction Fetch Unit • The common RTL operations • Fetch the Instruction: mem[PC] • Update the program counter: • Sequential Code: PC <- PC + 4 • Branch and Jump: PC <- “something else” Instruction Word 32

  18. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits RTL: The ADD Instruction • add rd, rs, rt • mem[PC] Fetch the instruction from memory • R[rd] <- R[rs] + R[rt] The actual operation • PC <- PC + 4 Calculate the next instruction’s address

  19. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits RTL: The Subtract Instruction • sub rd, rs, rt • mem[PC] Fetch the instruction from memory • R[rd] <- R[rs] - R[rt] The actual operation • PC <- PC + 4 Calculate the next instruction’s address

  20. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 3b: Add & Subtract • R[rd] <- R[rs] op R[rt] Example: addU rd, rs, rt • Ra, Rb, and Rw come from instruction’s rs, rt, and rd fields • ALUctr and RegWr: control logic after decoding the instruction Rd Rs Rt ALUctr RegWr 5 5 5 busA Rw Ra Rb busW 32 32 32-bit Registers Result ALU 32 32 busB Clk 32

  21. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Datapath for Register-Register Operations (in general) • R[rd] <- R[rs] op R[rt] Example: add rd, rs, rt • Ra, Rb, and Rw comes from instruction’s rs, rt, and rd fields • ALUctr and RegWr: control logic after decoding the instruction Rd Rs Rt ALUctr RegWr 5 5 5 busA Rw Ra Rb busW 32 32 32-bit Registers Result ALU 32 32 busB Clk 32

  22. Register-Register Timing Clk Clk-to-Q Old Value New Value PC Instruction Memory Access Time Rs, Rt, Rd, Op, Func Old Value New Value Delay through Control Logic ALUctr Old Value New Value RegWr Old Value New Value Register File Access Time busA, B Old Value New Value ALU Delay busW Old Value New Value Rd Rs Rt ALUctr Register Write Occurs Here RegWr 5 5 5 busA Rw Ra Rb busW 32 32 32-bit Registers Result ALU 32 32 busB Clk 32

  23. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 31 16 15 0 immediate 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 bits 16 bits RTL: The OR Immediate Instruction • ori rt, rs, imm16 • mem[PC] Fetch the instruction from memory • R[rt] <- R[rs] or ZeroExt(imm16) The OR operation • PC <- PC + 4 Calculate the next instruction’s address

  24. 11 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits rd? 31 16 15 0 immediate 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 bits 16 bits 3c: Logical Operations with Immediate • R[rt] <- R[rs] op ZeroExt[imm16] ] Rd Rt RegDst Mux Rs ALUctr RegWr 5 5 5 busA Rw Ra Rb busW 32 Result 32 32-bit Registers ALU 32 32 busB Clk 32 Mux ZeroExt imm16 32 16 ALUSrc

  25. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 31 16 15 0 0 immediate 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 bits 16 bits 31 16 15 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 immediate 16 bits 16 bits RTL: The Load Instruction • lw rt, rs, imm16 • mem[PC] Fetch the instruction from memory • Addr <- R[rs] + SignExt(imm16) Calculate the memory address R[rt] <- Mem[Addr] Load the data into the register • PC <- PC + 4 Calculate the next instruction’s address

  26. 11 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits rd 3d: Load Operations • R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16 Rd Rt RegDst Mux Rs ALUctr RegWr 5 5 5 busA W_Src Rw Ra Rb busW 32 32 32-bit Registers ALU 32 32 busB Clk MemWr 32 Mux Mux WrEn Adr Data In 32 Data Memory Extender 32 imm16 32 16 Clk ALUSrc ExtOp

  27. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 3e: Store Operations • Mem[ R[rs] + SignExt[imm16] <- R[rt] ] Example: sw rt, rs, imm16 Rd Rt ALUctr MemWr W_Src RegDst Mux Rs Rt RegWr 5 5 5 busA Rw Ra Rb busW 32 32 32-bit Registers ALU 32 32 busB Clk 32 Mux Mux WrEn Adr Data In 32 32 Data Memory Extender imm16 32 16 Clk ALUSrc ExtOp

  28. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 3f: The Branch Instruction • beq rs, rt, imm16 • mem[PC] Fetch the instruction from memory • Equal <- R[rs] == R[rt] Calculate the branch condition • if (COND eq 0) Calculate the next instruction’s address • PC <- PC + 4 + ( SignExt(imm16) x 4 ) • else • PC <- PC + 4

  29. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits Cond Rs Rt 4 RegWr 5 5 5 busA Adder Rw Ra Rb busW 32 32 32-bit Registers Equal? Mux PC busB Clk 32 Adder Clk Datapath for Branch Operations • beq rs, rt, imm16 Datapath generates condition (equal) Inst Address nPC_sel 32 00 imm16 PC Ext

  30. Inst Memory Adr Adder Mux Adder Putting it All Together: A Single Cycle Datapath Instruction<31:0> <21:25> <16:20> <11:15> <0:15> Rs Rt Rd Imm16 RegDst nPC_sel ALUctr MemWr MemtoReg Equal Rt Rd 0 1 Rs Rt 4 RegWr 5 5 5 busA Rw Ra Rb = busW 00 32 32 32-bit Registers ALU 0 32 busB 32 0 PC 32 Mux Mux Clk 32 WrEn Adr 1 Clk 1 Data In Extender Data Memory imm16 PC Ext 32 16 imm16 Clk ExtOp ALUSrc

  31. ALU PC Clk An Abstract View of the Critical Path • Register file and ideal memory: • The CLK input is a factor ONLY during write operation • During read operation, behave as combinational logic: • Address valid => Output valid after “access time.” Critical Path (Load Operation) = PC’s Clk-to-Q + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew Ideal Instruction Memory Instruction Rd Rs Rt Imm 5 5 5 16 Instruction Address A Data Address 32 Rw Ra Rb 32 Ideal Data Memory 32 32 32-bit Registers Next Address Data In B Clk Clk 32

  32. Binary Arithmetics for the Next Address • In theory, the PC is a 32-bit byte address into the instruction memory: • Sequential operation: PC<31:0> = PC<31:0> + 4 • Branch operation: PC<31:0> = PC<31:0> + 4 + SignExt[Imm16] * 4 • The magic number “4” always comes up because: • The 32-bit PC is a byte address • And all our instructions are 4 bytes (32 bits) long • In other words: • The 2 LSBs of the 32-bit PC are always zeros • There is no reason to have hardware to keep the 2 LSBs • In practice, we can simply the hardware by using a 30-bit PC<31:2>: • Sequential operation: PC<31:2> = PC<31:2> + 1 • Branch operation: PC<31:2> = PC<31:2> + 1 + SignExt[Imm16] • In either case: Instruction Memory Address = PC<31:2> concat “00”

  33. PC 0 Adder Mux 1 Adder Clk Next Address Logic: Expensive and Fast Solution • Using a 30-bit PC: • Sequential operation: PC<31:2> = PC<31:2> + 1 • Branch operation: PC<31:2> = PC<31:2> + 1 + SignExt[Imm16] • In either case: Instruction Memory Address = PC<31:2> concat “00” 30 Addr<31:2> 30 Addr<1:0> “00” 30 Instruction Memory 30 “1” 32 30 SignExt 30 imm16 16 Instruction<15:0> Instruction<31:0> Branch Zero

  34. PC 0 Adder Mux Clk 1 Next Address Logic: Cheap and Slow Solution • Why is this slow? • Cannot start the address add until Zero (output of ALU) is valid • Does it matter that this is slow in the overall scheme of things? • Probably not here. Critical path is the load operation. 30 Addr<31:2> 30 “1” Addr<1:0> “00” Carry In Instruction Memory “0” 30 32 SignExt imm16 30 30 16 Instruction<15:0> Instruction<31:0> Branch Zero

  35. 31 26 0 op target address 6 bits 26 bits RTL: The Jump Instruction • j target • mem[PC] Fetch the instruction from memory • PC<31:2> <- PC<31:28> concat target<25:0> Calculate the next instruction’s address

  36. 1 Mux PC 0 0 Adder Mux 1 Adder Clk Instruction Fetch Unit • j target • PC<31:2> <- PC<31:28> concat target<25:0> 30 Addr<31:2> 30 PC<31:28> Addr<1:0> “00” 4 Target Instruction Memory 30 Instruction<25:0> 26 30 32 30 “1” Jump Instruction<31:0> 30 SignExt 30 imm16 16 Instruction<15:0> Branch Zero

  37. Putting it All Together: A Single Cycle Datapath • We have everything except control signals (underline) Instruction<31:0> Branch Instruction Fetch Unit Jump Rd Rt <21:25> <16:20> <11:15> <0:15> Clk RegDst 1 0 Mux Rt Rs Rd Imm16 Rs Rt RegWr ALUctr 5 5 5 MemtoReg busA Zero MemWr Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc ExtOp

  38. ALU PC Clk An Abstract View of the Implementation • Logical vs. Physical Structure Control Ideal Instruction Memory Control Signals Conditions Instruction Rd Rs Rt 5 5 5 Instruction Address A Data Address Data Out 32 Rw Ra Rb 32 Ideal Data Memory 32 32 32-bit Registers Next Address Data In B Clk Clk 32 Datapath

  39. Summary • 5 steps to design a processor • 1. Analyze instruction set => datapath requirements • 2. Select set of datapath components & establish clock methodology • 3. Assemble datapath meeting the requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. • 5. Assemble the control logic • MIPS makes it easier • Instructions same size • Source registers always in same place • Immediates same size, location • Operations always on registers/immediates • Single cycle datapath => CPI=1, CCT => long • Next time: implementing control (Steps 4 and 5)

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