Carlos Arthur Lang Lisbôa, Erik Schüler , Luigi Carro SRC TechCon 2005

1. Dealing with Multiple Simultaneous Faults in Future Technologies INFORMÁTICA Carlos Arthur Lang Lisbôa, Erik Schüler , Luigi Carro SRC TechCon 2005 Basic Concepts • the multiplier generates a bit stream in which the number of bits equal to 1 is the value of the product • adding signal redundancy to this bit stream, tolerance to multiple bit flips in the stream is achieved • the stream is tolerant to a “balance” of flips which depends on the redundancy added to the stream (see Table 1) Bit Stream Representation of Products Table 1. Redundant Bits x Fault Tolerance Comments • the exact sum of values represented by bit streams can be obtained simply by concatenating the streams corresponding to the values of the summands • as long as the values are kept as streams, they are protected against faults F1 F1 F1 2 1 0 x F2 F2 F2 2 1 0 . . . F2 F1 F2 F1 F2 F1 0 2 0 1 0 0 . . . F2 F1 F2 F1 F2 F1 1 2 1 1 1 0 . . . F2 F1 F2 F1 F2 F1 2 2 2 1 2 0 5-tap Filter using RobOps b48 .. b33 b32 .. b17 b16 .. b5 b4 .. b1 b0 • Notes: • “r” may be an odd number • fault tolerance does not depend on the factors’ width (f); it depends on “r” • the total quantity of bits that can change to 1 (w/o matching complementary flips) is 2r-1-1 • the total quantity of bits that can change to 0 (w/o matching complementary flips) is 2r-1 Fig. 1 – Proposed Multiplication Algorithm - bit stream product (the count of 1’s in the stream is equal to the product value) cctr cctr cctr cctr cctr cctr cctr cctr cctr cctr cctr cctr cctr cctr cctr Sample 8-bit Stream Multiplier (RobOp) b48 .. b48 b47 .. b47 ... b0 .. b0 1 1 1 1 0 0 0 8 times 8 times 8 times +4 total count of 1’s = 8 * product + 4 converter 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 Vdd a b 7.1 6.1 5.1 4.1 3.1 2.1 1.1 0.1 Fig. 2 – Adding robustness to the bit stream through redundancy 7.2 6.2 5.2 4.2 3.2 2.2 1.2 0.2 • 5 robust multipliers generate 75 (5 x 15) product column streams • each column in the filter shares the same 4 redundant bits (bits = 1) • combinational circuits (cctr) count bits equal to 1 in each column stream • 2 lsbits of the counters are discarded (pseudo division by 4) • converter circuit adds bit counts from each column (according to their weights), thus generating the binary coded filter output • product streams stand up to 3 bit flips in each column • conversion from bit streams to binary code (counters and adders) not yet protected 7.3 6.3 5.3 4.3 3.3 2.3 1.3 0.3 7.4 6.4 5.4 4.4 3.4 2.4 1.4 0.4 7.5 6.5 5.5 4.5 3.5 2.5 1.5 0.5 12 a.b a.b a.b a.b a.b a.b a.b a.b 1 1 1 1 7.6 6.6 5.6 4.6 3.6 2.6 1.6 0.6 7.7 6.7 5.7 4.7 3.7 2.7 1.7 0.7 • 64 robust 1-bit multipliers (see detail) generate the 15 “column bit streams” • total of 512 AND gates (64 multipliers x 8 gates) • each column stream is independent from those of the other columns (different weights) • each column stream has 8 to 64 data bits plus 4 bits equal to 1 (see detail) • total of 572 output bits (512 + 15 x 4) • conversion to binary code (counting bits equal to 1 in the stream) postponed Porto Alegre - RS BRAZIL Phone +55 51 33166155 e-mail calisboa@inf.ufrgs.br eschuler@eletro.ufrgs.br carro@eletro.ufrgs.br Universidade Federal do Rio Grande do Sul - UFRGS Instituto de Informática, Pós-Graduação em Ciência da Computação Grupo de Microeletrônica (GME) Laboratório de Sistemas Embarcados (LSE) http://www.inf.ufrgs.br/gme, http://www.inf.ufrgs.br/~lse Using Bit Stream Operators(2, 3, 4) Application Using the robust multiplier to build a 5-tap FIR filter • Conversion from bit streams to binary coded values • Current implementation • minimum area • not protected against multiple simultaneous faults • Future implementation • keep the minimum area architecture • use of n-MR with fault tolerant voter Conclusions • the main drawback of this approach is that the size of the bit streams grows very fast, but this should be ok for SET, for example • further research is being conducted in order to develop circuits to convert the streams into binary values with tolerance to multiple simultaneous faults (2) Lisbôa, C. and Carro, L., “Arithmetic Operators Robust to Multiple Simultaneous Upsets”, in Proceedings of the 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - DFT 2004, pp. 289-297, ISBN 0-7695-2241-6. IEEE Computer Society, New York, October 2004. (3) Lisbôa, C. and Carro, L., “Highly Reliable Arithmetic Multipliers for Future Technologies”, in Proceedings of the International Workshop on Dependable Embedded Systems - WDES 2004 - in conjunction with the 23rd International Symposium on Reliable Distributed Systems - SRDS 2004, pp. 13-18. Edited by Becker, L. B. and Kaiser, J., Florianópolis, October 17, 2004. (4) Lisbôa, C., Carro, L., and Cota, E. “RobOps – Arithmetic Operators for Future Technologies”, in Informal Proceedings of the 10th IEEE European Test Symposium (ETS 05), Tallinn, Estonia, May 2005.