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Digital Logic & Design Vishal Jethva Lecture 13

Digital Logic & Design Vishal Jethva Lecture 13. Recap. Functions having multiple outputs Comparator Quine-McCluskey Method (two variations) Odd-Prime Number checker circuit. Odd Prime Number (table1). Odd Prime Number (table2). Odd Prime Number (table3). Odd Prime Number (table3).

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Digital Logic & Design Vishal Jethva Lecture 13

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  1. Digital Logic & Design Vishal Jethva Lecture 13 SVBITEC.WORDPRESS.COM

  2. Recap • Functions having multiple outputs • Comparator • Quine-McCluskey Method (two variations) • Odd-Prime Number checker circuit SVBITEC.WORDPRESS.COM

  3. Odd Prime Number (table1) SVBITEC.WORDPRESS.COM

  4. Odd Prime Number (table2) SVBITEC.WORDPRESS.COM

  5. Odd Prime Number (table3) SVBITEC.WORDPRESS.COM

  6. Odd Prime Number (table3) SVBITEC.WORDPRESS.COM

  7. Odd Prime Number (table4) SVBITEC.WORDPRESS.COM

  8. Odd Prime Number (table5) SVBITEC.WORDPRESS.COM

  9. Combinational Logic • Implementation of SOP using AND-OR • Implementation of POS using OR-AND SVBITEC.WORDPRESS.COM

  10. SOP Implementation SVBITEC.WORDPRESS.COM

  11. POS Implementation SVBITEC.WORDPRESS.COM

  12. Design and Implementation of Digital Circuits • Function Table • Simplification of Expression • Implementation SVBITEC.WORDPRESS.COM

  13. Adjacent 1s Detector Circuit • SOP Implementation • Directly from function table • Simplified implementation • Implementation using NAND gates SVBITEC.WORDPRESS.COM

  14. Adjacent 1s Detector Function SVBITEC.WORDPRESS.COM

  15. SOP Implementation SVBITEC.WORDPRESS.COM

  16. SOP Expression Simplification SVBITEC.WORDPRESS.COM

  17. SOP based Simplified Circuit SVBITEC.WORDPRESS.COM

  18. NAND based Implementation SVBITEC.WORDPRESS.COM

  19. Adjacent 1s Detector Circuit • POS Implementation • Directly from function table • Simplified Implementation • Implementation using NOR Gates SVBITEC.WORDPRESS.COM

  20. POS Implementation SVBITEC.WORDPRESS.COM

  21. POS Expression Simplification SVBITEC.WORDPRESS.COM

  22. POS based Simplified Circuit SVBITEC.WORDPRESS.COM

  23. NOR based Implementation SVBITEC.WORDPRESS.COM

  24. Operation of Circuit • Represented through a timing diagram • Timing diagram of 8 time intervals • Each interval representing a new input SVBITEC.WORDPRESS.COM

  25. POS based Simplified Circuit SVBITEC.WORDPRESS.COM

  26. Operation of Circuit SVBITEC.WORDPRESS.COM

  27. Active low/high inputs/outputs • Active output state represented by 1 or 0 • Active input state represented by 1 or 0 • A bubble at output represents active low output • A bubble at input represents active low input SVBITEC.WORDPRESS.COM

  28. Active low/high inputs/outputs SVBITEC.WORDPRESS.COM

  29. Active-high inputs & outputs SVBITEC.WORDPRESS.COM

  30. Active-high inputs & outputs SVBITEC.WORDPRESS.COM

  31. Operation of Circuit SVBITEC.WORDPRESS.COM

  32. Odd-Parity Generator Circuit • Circuit checks the 4-bit data • Generates a parity bit (odd) • Data + parity bit add up to odd number of 1s SVBITEC.WORDPRESS.COM

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