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EE434 ASIC & Digital Systems

EE434 ASIC & Digital Systems. Jacob Murray School of EECS Washington State University jmurray@eecs.wsu.edu. Lecture 11 Physical Design Issues. Interconnect Scaling Effects. Dense multilayer metal increases coupling capacitance Older Assumption Deep sub-micron

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EE434 ASIC & Digital Systems

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  1. EE434ASIC & Digital Systems Jacob Murray School of EECS Washington State University jmurray@eecs.wsu.edu

  2. Lecture 11 Physical Design Issues

  3. Interconnect Scaling Effects • Dense multilayer metal increases coupling capacitance Older Assumption Deep sub-micron • Long/narrow line width further increases resistance of interconnect

  4. Wire Modeling

  5. Elmore Delay • Follow board notes

  6. Elmore Delay

  7. Delay of a wire

  8. FO4 vs. Wire Delay 3mm 2mm 1mm FO4

  9. Buffer Insertion for Long Wires • Make Long wires into short wires by inserting buffers periodically. • Divide interconnect into N sections as follows: • Then delay through buffers and interconnect is given by: tp = N *[Reff(Cself+ CW/2) + (Reff + RW)(CW/2+Cfanout)] • What is the optimal number of buffers? Find N such that tP/ N = 0  N  sqrt(0.4RintCint L2 /tpbuf) where tpbuf = Reff(Cself + Cfanout) • What size should the buffers be? Find M such that tP/ M = 0  M = sqrt((Reqn/Cg3W)(Cint/Rint)) M M Rw Rw M M Rw Rw 2W W Cw/2 Cw/2 Cw/2 Cw/2 Reff = Reqn/M Cself=Cj3W*M Cfanout = Cg3W*M Rw = RintL/N Cw = CintL/N

  10. Global wire delay Global wires limit system performance

  11. Purpose of Power Distribution • Goal of power distribution system is to deliver the required current across the chip while maintaining the voltage levels necessary for proper operation of logic circuits • Must route both power and ground to all gates • Design Challenges • How many power and ground pins should we allocate? • Which layers of metal should be used to route power/ground? • How wide should we make the wire to minimize voltage drops and reliability problems? • How do we maintain VDD and GND within noise budget? • How do we verify overall power distribution system?

  12. < Vdd Vdd n4 n3 < Vdd n2 n1 n8 n5 n6 n7 Power Distribution Issues - IR Drop • Narrow line widths increase metal line resistance. • As current flows through power grid, voltage drops occur. • Actual voltage supplied to transistors is less than Vdd. • Impacts speed and functionality • Need to choose wire widths to handle current demands of each segment

  13. Power Grid Issues - Electromigration • As current flows down narrow wires, metal begins to migrate • Metal lines break/thin over time due to metal fatigue • Based on average/peak current density • Need to widen wires enough to avoid this phenomenon n4 n3 n2 n1 n8 n5 n6 n7

  14. Power Routing Examples Block A Block B Block A Block B Single Trunk Multiple Trunks

  15. Simple Routing Examples Block A Block B Block A Block B Double-Ended Connections Wider Trunks

  16. Interleaved Power/Ground Routing Interleaved Vdd/Vss

  17. L*di/dt Effects in the Power Supply • In addition to IR drop, power system inductance is also an issue. • Inductance may be due to power pin, power bump or power grid. • Overall voltage drop is: Vdrop = IR + Ldi/dt • Distribute decoupling capacitors (decaps) liberally throughout design • Capacitors store up charge • Can provide instantaneous source of current for switching

  18. Clock Design Issues

  19. Sources of clock skew

  20. Power Dissipation in Clocks

  21. Reducing Power in Clocking • Gated Clocks: • can gate clock signals through AND gate before applying to flip-flop; this is more of a total chip power savings • all clock trees should have the same type of gating whether they are used or not, and at the same level - total balance • Reduce overall capacitance (again, shielding vs. spacing) (a) higher total cap./less area (b) lower cap./ more area • Tradeoff between the two approaches due to coupling noise • approach (a) is better for inductive noise; (b) is better for capacitive noise Signal 1 clock Signal 2 shield clock shield

  22. Clock Tree Configurations • Minimal area cost • Requires clock-tree management • Use a large super buffer to drive downstream buffers • Balancing may be an issue Tree Secondary clock drivers Multi-stage clock tree Main clock driver

  23. Clock Tree Configurations H-Tree • Place clock root at center of chip and distribute as an H structure to all areas of the chip • Clock is delayed by an equal amount to every section of the chip • Local skew inside blocks is kept within tolerable limits

  24. Clock Tree Configurations Grid • Greater area cost • Easier skew control • Increased power consumption • Electromigration risk increased at drivers • Severely restricts floorplan and routing

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