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EE434 ASIC & Digital Systems

EE434 ASIC & Digital Systems. Jacob Murray School of EECS Washington State University jmurray@eecs.wsu.edu. Lecture 8. Implementation Methodology. Some of the slides are adopted from Digital Integrated Circuits by Jan M Rabaey. Digital Circuit Implementation Approaches. Custom.

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EE434 ASIC & Digital Systems

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  1. EE434ASIC & Digital Systems Jacob Murray School of EECS Washington State University jmurray@eecs.wsu.edu

  2. Lecture 8 Implementation Methodology Some of the slides are adopted from Digital Integrated Circuits by Jan M Rabaey

  3. Digital Circuit Implementation Approaches Custom Semicustom Cell-based Array-based Standard Cells Pre-diffused Pre-wired Ma cro Cells Compiled Cells (Gate Arrays) (FPGAs) Implementation Choices

  4. Array-based Pre-diffused Pre-wired (Gate Arrays) (FPGAs) Late-Binding Implementation

  5. Gate Array — Sea-of-gates Uncommitted Cell • Wafers containing arrays of cells Committed Cell(4-input NOR) Interconnections • Actual Design

  6. Oxide-isolation PMOS PMOS NMOS NMOS NMOS Sea-of-gate Primitive Cells Using gate-isolation Using oxide-isolation

  7. Sea-of-gates Committed SOG Logic Memory Subsystem LSI Logic LEA300K (0.6 mm CMOS) Courtesy LSI Logic

  8. Prewired Arrays Classification of prewired arrays (or field-programmable devices) • Programmable Logic Style • Array-Based • Look-up Table • Based on Programming Technique (switching) • Fuse-based (program-once) PROM • Non-volatile EPROM based • RAM based • Programmable Interconnect Style • Channel-routing • Mesh networks

  9. Two-Level Logic Every logic function can beexpressed in sum-of-productsformat (AND-OR) minterm Inverting format (NOR-NOR) more effective

  10. Or-Plane And-Plane V f GND DD PLA Layout – Exploiting Regularity

  11. I I I I I I 5 4 3 2 1 0 Programmable I I I I 3 2 1 0 I I I I I I OR array 5 4 3 2 1 0 Fixed AND array O O O O O 3 2 1 0 O 0 0 Indicates programmable connection Indicates fixed connection Array-Based Programmable Logic Programmable OR array Fixed OR array Programmable AND array Programmable AND array O O O O O O 3 2 1 3 2 1 PLA PROM PAL

  12. Implementing functions with PLA

  13. 1 X X X 2 1 0 : programmed node NA NA f f 1 0 Programming a PROM

  14. PAL 16R8

  15. More Complex PAL • Higher capacity devices • Single PAL architecture is not feasible • Programmable logic planes grow too quickly Multiple PALs integrated together Complex Programmable Logic Device (CPLD)

  16. CPLD

  17. Altera CPLD • Array of Logic Array Blocks (LABs) • Programmable Interconnect Array (PIA): Array of interconnect wires • LAB I/O ←PIA→ LAB I/O • Chip I/O ↔ PIA • Chip I/O ↔ LABs MAX 7000

  18. MAX 7000 Macrocell

  19. AMD - CPLD AMD Mach 4 CPLD

  20. FPGAs

  21. Configuration A B S F= 0 0 0 0 0 X 1 X 0 Y 1 Y 0 Y X XY X 0 Y XY Y 0 X XY Y 1 X X Y + 1 0 X X 1 0 Y Y 1 1 1 1 2-input MUX as programmable logic block A 0 F B 1 S

  22. Implementing Logic functions with LUTs • Each logic blockin an FPGA has a small number of inputs and outputs • The most commonly used logic block is a lookup table (LUT), which contains storage cells that are used to implement a small logic function

  23. Two-input LUT

  24. In Out Out 00 0 01 1 10 1 Memory 11 0 ln1 ln2 LUT-Based Logic Cell

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