Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels

1. Spice-Accurate SystemC Macromodels of Noisy on-Chip Communication Channels Alessandro Bogliolo University of Urbino Nicola Terrassan and Davide Bertozzi University of Ferrara

2. Outline • Motivation • Physical channel design • Analytical model • Design • Validation against HSPICE • Macromodel integration in SystemC • Accuracy assessment • Applications and conclusions

3. Motivation SPICE-based design space explorations are not viable due to system complexity 500M Transistor Platform Development of accurate physical models and their abstraction into accurate compact models are mandatory for designing complex circuits Design-Productivity Gap • Degradation of RC propagation delay across on-chip interconnects • Low-swing signaling and coding for low-power • Increased sensitivity to on-chip noise sources Physical gap Hell of nano-scale physics

4. Objective of the work FF in FF out Driver Receiver RC line Data in Data out • Communication channel • driver, interconnect, receiver, sampling stages • Target: 1 GHz operating frequency, low-power, high throughput links • Scalability analysis • From 130 to 90 nm, Berkeley Predictive Technology Models • Analytical model • capturing the effects of on-chip noise sources on the channel sub-systems • based on the noise sensitive area concept Paramet. bit-level model of noisy on-chip communication channels Macromodel integration in SystemC for system-level simulation

5. Outline • Motivation • Physical channel design • Analytical model • Design • Validation against HSPICE • Macromodel integration in SystemC • Accuracy assessment • Applications and conclusions

6. Pseudo-differential interconnect PDIFF receiver RC Line Driver Static FF Clocked sense amplifier • Makes use of a single wire per bit while still retaining most advantages of differential signaling: low swing, low sensitivity to supply noise • Sources of reliability degradation: mismatches of input pair TNs or REFs

7. Delay breakdown 130nm technology node Transistor sizing with Hspice optimization engine Vdd=1.2V, Swing=0.2V Interconnect length=2mm (intermediate metal layer) • Maximum Frequency: 1.35Ghz • SAFF Flip Flop and PDIFF receiver are the delay bottlenecks

8. Delay scalability • 130 nm technology node • Vdd = 1,2 V • Swing = 0,2 V • Interconnect length = 2 mm • Intermediate metal layer • FMAX (130 nm)= 1,35 GHz • 90 nm technology node • Vdd = 1 V • Swing = 0,2 V (to preserve noise margins) • Interconnect length = 2 mm • Intermediate metal layer • FMAX (90 nm)= 1,45 GHz Propagation delay. Logic 1-to-0 transition • Scaling of gate delay • Interconnect delay does not scale (51% degradation)

9. Power breakdown 130nm 90nm 7% 10% 19% 30% SAFF 26% 24% Driver RC line PDIFF 27% Latch NOR 7% 20% 30% Total Power: 98,968 µW 38,532 µW • Scaling factor of power ranges from 0.24x (SAFF) to 0.52x (NOR Latch) • Interconnect power increases by 1.1x • FF, driver and receiver are the most power-hungry components • Interconnect power relevant only in 90nm • Overall channel power reduces by 60%

10. Outline • Motivation • Physical channel design • Analytical model • Design • Validation against HSPICE • Macromodel integration in SystemC • Accuracy assessment • Applications and conclusions

11. Driver Receiver RC line Data in FF in FF out Data out Modelling approach splitting the communication channel in two parts: a driving section and a driven section Splitting point Driving section Driven section Poses conditions to its shape to guarantee correct sampling Provides a signal waveform Error probability evaluated by comparing the signal provided by the driving section with the requirements posed by the driven section

12. Vin Receiv. FF clock Noise sensitive areas Receiver requirements modelled through noise sensitive areas: regions in the signal-time plane which are forbidden to the signal waveform Vin Vswing=0.2 t0 Hold Time Triggering condition: a requirement on the input voltage at sampling time SA-based receiver imposes holding requirements on the input signal: the stronger the signal the shorter the hold time

13. Experimental NSA nominal 130 nm technology node – 10% positive injected noise on Vdd Vin [V] Thold [ps] • A positive Vdd variation at the receiver shrinks the NSA • The receiver takes less time to sample input signals • Triggering condition reduces to: • Vin higher than 0.140V (for sampling a logic 1) • Vin lower than 0.065V (for sampling a logic 0)

14. Parametric NSA model Measured parameters are manipulated in order to use linear regressions to fit experimental data with a minimum number of fitting coefficients

15. Model accuracy • Analytical models of Thold evaluated for different random combinations of noise sources and Vin values • HSPICE sweep simulations conducted with injected noise sources to determine the minimum hold time • Results: • Average error: 3.5% in 130 nm (4.95% in 90nm) • Maximum error: 17.53% in 130 nm (23.5% in 90nm) for concurrent common-mode noise on Vref and Vgnd

16. FF in Driver RC line Data in Vin Far-End Voltage (mV) Time (ps) Driving subcircuit model Far-end signal waveform approximated by a delay followed by anexponential transient

17. Exponential transient model Logic 0 to 1 transition Logic 1 to 0 transition c is the slope parameter, experimentally approximated by: Almost insensitive to Vref variations Depends on interconnect length (l) Further refined to account for wire parameters: Rw,Cw: resistance and capacitance per unit length Rt: driver output resistance Cr: receiver input capacitance

18. Directly proportional to Resistance and Capacitance per unit length Inversely proportional to Vdd - Gnd Delay model We did not derive fitting models of the delay measured from HSPICE simulations, but of those delay values that minimize the MSE of the fitting exponential transients We therefore aim at achieving maximum accuracy in predicting the far-end voltage Vin at sampling time

19. Accuracy Validation against HSPICE for different noise scenarios MSE for exp. transient In practice, the error on Vin is much smaller than MSE at sampling time Far-End Voltage (mV) Time (ps)

20. Outline • Motivation • Physical channel design • Analytical model • Design • Validation against HSPICE • Macromodel integration in SystemC • Accuracy assessment • Applications and conclusions

21. Macromodel integration in SystemC Need: expose the analytical models to a high-level modelling and simulation environment • Interconnect analysis with SPICE accuracy in complex systems • Traditional macromodels integrated in VHDL/Verilog • SystemC is emerging as the ref. backbone for system-level design • C-language programming facilitates HW-SW codesign Analytical macromodel integration in SystemC We exploited the Advanced and Flexible Communication Abstractions in SystemC • Ports: gateways to communication functions • Interfaces: declaration of communication functions • Channels: actual implementation of communication functions

22. HW Module HW Module SystemC communication abstractions Plug-and-play channels in the link communication model Predefined sc_signal channel (read/write implementation) Interface Interface Plug-'n'-Play sc_signal with Integrated Analytical model Input port Output port Predefined channel augmented with analytical model

23. SystemC vs SPICE accuracy Spice SystemC Accuracy results for 30 different mixes of noise sources • Average error at sampling time never worse than 2%, max. error less than 7% • Risk of logic value misprediction if sampled voltage close to decision threshold • a warning is generated by the SystemC channel • Accounting for Inter-Symbol Interference • Simulation time improvements with SystemC by 10x

24. Outline • Motivation • Physical channel design • Analytical model • Design • Validation against HSPICE • Macromodel integration in SystemC • Accuracy assessment • Applications and conclusions

25. Communication channel exploration First application Injection of noise in the transmitter until a logic error is produced at the receiver Power supply noise FF TX

26. Communication channel exploration Second application: Exploration of different clocking schemes Native dual clocking schemes with phase shift 1000 ps = 1 GHz Clock TX Clock RX Which is the min. shift for correct sampling at 1 GHz? SystemC35ps HSPICE35ps (exact matching)

27. Conclusions • Design of a communication channel for high-performance on-chip links • targeting 1 GHz operating frequency at 130nm and 90nm techn. nodes • low power, low swing signaling • Analytical modelling of channel behavior in presence of noise • Noise sensitive area concept, delay and signal slope models • Macromodel integration into SystemC • Powerful communication abstractions • Plug-and-play backannotated channel • Very high accuracy in predicting far-end voltage at sampling time • Average error below 2%, max error below 7% • Improvement of simulation time by 10x • Accounting for Inter-Symbol Interference • Macromodels at work for fast • assessment of channel robustness against noise sources • physical channel design space exploration • Future work: crosstalk analytical macromodelling