Challenges in Hardware Logic Verification

1. Challenges in Hardware Logic Verification Bruce Wile IBM Server Group Verification Lead 10/25/01

2. Agenda • Five Challenges in Verification • Future Verification Trends

3. Testcase Generators Billions of Sim cycles + = Server Farm (Batch pool) 5 Challenges in Verification 1. Better use of available simulation cycles

4. Bug discovery rate 5 Challenges in Verification 1. Better use of available simulation cycles Use coverage metrics to increase new path testing.

5. State Machines Timing diagrams ack will come on after the bias signal, followed in two cycles by the NOT MY 5 Challenges in Verification 2. Specification methodology

6. Logic Description 5 Challenges in Verification 2. Specification methodology Simulation Formal Verification Model Checking

7. 5 Challenges in Verification 3. Power verification

8. Turn off units when not in use Verify "not in use" and no clocking Measure switching factor in chip and in "hot areas" during sim and benchmarks. Low power micro- arch design and design changes 5 Challenges in Verification 3. Power verification Function Check

9. Self-optimizing Self-configuring Self-protecting Self-healing 5 Challenges in Verification 4. Error path testing in self healing systems

10. 5 Challenges in Verification 4. Error path testing in self healing systems For all of the legal paths for which the design must be verified, there's an order of magnitude more "illegal" paths. Verification must ensure that the hardware can: • Recover and continue, or • Take itself off-line

11. Buffer Queue P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P Memory Memory Memory Memory I/O I/O I/O I/O Interrupt When processor receives I/O interrupt it can't move forward until buffer releases address X, but buffer can't move forward until interrupt is completed.... 5 Challenges in Verification 5. Detecting System Deadlocks anyServer

12. P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P Memory Memory Memory Memory I/O I/O I/O I/O 5 Challenges in Verification 5. Detecting System Deadlocks anyServer One solution: Abstract (hi-level) model using "Protocol" (Formal) verification to search for hangs

13. Random Testcase Gen FV Deterministic 5 Challenges in Verification 5. Choosing the right verification technology Multiple technologies to choose from, But, few experts in all

14. 5 Challenges in Verification 5. Choosing the right verification technology Education Experience in the verification cycle Strong Verification career path Continuing challenges

15. Agenda • Five Challenges in Verification • Future Verification Trends

16. I-Stream Generator BHT Array Loader Instruction Unit and Pipe Behavioral (checking and Driving BHT Control Logic and BHT Array (Design under Test) BHT Array Shadow (Checking) Automatic modification of random parameters based on observed coverage Future Verification Trends • Coverage Directed Testcase Generation

17. Logic Description Future Verification Trends • Integration of Simulation with Formal Verification Simulation Formal Verification Model Checking

18. Logic Description Integration control Future Verification Trends • Integration of Simulation with Formal Verification Simulation Formal Verification Model Checking

19. Bus Architecture FPU InfiniBand Future Verification Trends • Sharing of verification I.P. anyServer P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P Memory Memory Memory Memory I/O I/O I/O I/O

20. Future Verification Trends • Sharing of verification I.P. • SOC Design will lead sharing of Verification IP • Components come from multiple sources • Need to supply verification IP • Need to have standard backplane • Need standard constructs