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Submicron Verification Challenges

Submicron Verification Challenges. Uri Gruenbaum. Presentation Flow Chart. Intro. Intro. @speed. Problems. Case study. Presentation Progress. Intro. @speed. Problems. Case study. Intro. Intro. What’s going on? IC features continue to shrink. Fabrication processes under 130 nm

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Submicron Verification Challenges

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  1. SubmicronVerificationChallenges Uri Gruenbaum

  2. Presentation Flow Chart Intro Intro @speed Problems Case study

  3. Presentation Progress Intro @speed Problems Case study

  4. Intro Intro What’s going on? • IC features continue to shrink. • Fabrication processes under 130 nm • Different size generate different faults. • The faults Distribution is different • Good old Stuck-at pattern isn't Good enough. @Speed Competition Case study

  5. Intro Intro In 180 nm we had: • Stack at pattern • Standard memory BIST (Built in self test) • Iddq You combine all of them and you get a coverage of ~100% @speed problems Case study

  6. Intro Intro In 130 nm and less we have: • Higher frequencies. • Different physical properties. • Much more timing defects @speed problems Case study

  7. Intro Intro Did you know? • Research from LSI Logic and Intel shows that the population of timing defects for nanometer designs is ~2% @speed problems Case study

  8. Intro Intro Example: • 130 nm fabrication process • Yield average of 70% • Static fault testing coverage of 100% • 2% left unchecked… • 50% of them on average are ok • We will have a defect rate of 0.7% • DPM of 7000 @speed problems Case study Unacceptable

  9. Presentation Progress Intro @speed Problems Case study

  10. @speed Intro Background • Been available for many years • A timing defect test pattern • Used so far to test very high speed devices & very accurate goals @speed problems Case study

  11. @speed-before scan Intro @speed Competition Our Solution What next? clock

  12. @speed- scan insertion Intro @speed Competition Our Solution What next? SI SO SE clock

  13. 0 1 0 1 1 1 0 1 @speed-shift phase Intro @speed problems Case study SI 1 SO SE = 1 clock SI clock

  14. 1 0 1 SI SO SE = 1 clock 1 0 1 SI clock @speed-shift phase Intro @speed problems Case study

  15. A B C 1 0 1 SI A B C SO SE = 0 clock 1 0 1 SI clock @speed-capture Intro @speed problems Case study

  16. A B C A B C SI SO SE = 0 clock 1 0 1 SI clock @speed-capture Intro @speed problems Case study

  17. A B C C SI 0 A B SO SE = 1 clock 1 0 1 SI clock @speed-shift phase Intro @speed Problems Case study 0

  18. @speed Vs Stuck at Intro @speed problems Case study

  19. @speed-Accurate clocks Intro @speed • There can be variations between the testers clock and the PLL clocking problems Case study

  20. @speed - solution Intro • One solution is having the ATPG (automatic test pattern generation) to decide which clock is necessary @speed problems Case study

  21. Presentation Progress Intro Market Problems Case study

  22. Problems Intro • Test patterns for transition faults are not as efficient as for stuck at faults • Transition faults test = 5 times in size as a static fault test • When combined ,expensive tester reloads is performed Market Problems Case study

  23. Problems Intro An interesting fact: Market Problems Case study • Transition test pattern detect a significant percentage of stack at faults Starting to get the picture?

  24. Problems Intro • If you need to add TFP reduce the number of SAP. • Do it by creating the TAP first and the SAP next. Market Problems Case study

  25. Presentation Progress The Need @speed Problems Case study

  26. Case study The Need The goal: Getting the best possible test coverage without doing expensive tester memory reloads. Market problems Case study

  27. Case study The Need Characteristic of test design: Market problems Case study

  28. Case study The Need For the design, the test requirements are : Market • Tester can hold up to 10,000 test patterns • The highest priority is to get max coverage for SAF • The test coverage for the TF must be as high as possible as long as it still fits the memory. problems Case study

  29. Case study The Need Result: Market problems Case study

  30. Case study The Need • Truncating the TDF results in a significant lost in transition coverage • TDF coverage 85.14% 63.93% • Clearly not ideal Market problems Case study

  31. Case study The Need How can we improve it? Market problems • Recognize that for each TDF its equivalent SAF is also detected • remove the least effective patterns Case study

  32. Case study The Need Result: Market problems Case study

  33. Case study The Need Market problems Case study

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