Student : Andrey Kuyel Supervised by Mony Orbach Spring 2011 Final Presentation

1. Technion - Israel institute of technology department of Electrical Engineering High speed digital systems laboratory High-Throughput FFT Student : Andrey KuyelSupervised by Mony OrbachSpring 2011Final Presentation

2. Presentation overview • Project motivation and goals • Theory studding • FFT 16/32 core definitions • Encountered problems • Selecting optimal algorithm • FFT core design and development • Validation and verification • Xilinx development boar Demo

3. Project goals The project goals is to design and implement on FPGA device FFT that capable to deal with high rate data processing (rates up to 10MSamp/sec*). The design will be written on VHDL and tested on Xilinx development board. The project has aspects of: signal processing and logic design and high rate data processing. *- 5Ms/sec for each of I and Q components .

4. FFT - Theoretic overview The DFT (N- length vector) definition is: The time-complexity of the DFT is: The FFT algorithm (developed at first by J.W. Cooley and John Tukey at 1965) comes to reduce the time-complexity of DFT into This algorithm called: "The Cooley–Tukey radix-2 FFT algorithm". It is one of the most common FFT algorithms.

5. Radix 4 algorithm

6. Studding and Examining different FFT parallel algorithms The FFT (N=8) radix 2 data flow The FFT (N=16) radix 2 data flow Sixteen-point radix-4 decimation-in-time algorithm Length-16, Decimation-in-Frequency, In-order input, Radix-4 FFT

7. FFT core features FFT core will have the following features: • Real and imaginary Inputs: 8 bits width each. • Real and imaginary outputs: 20bits width each, where 12 MSB bits for integer part and 8 LSB bits for fractional part. • Drop-in module for Virtex-6 (xc6vlx240T) • Forward complex FFT • Transform sizes N = 16/32 • Arithmetic type: Fixed-point • Truncation after the butterfly • natural Input/output order • Input data at frequency 10 Ms/sec (total rate of real and image part of data )

8. FFT core general schematics Done Clock 16 points Complex Parallel FFT Start Edone rst fx0_re x0_re FFT Real data out 20q8 Real part Data input [7:0] x16 x16 fx15_re x15_re y0_im Imaginary part Data input [7:0] x16 fy0_im y15_im FFT Imag Data out 20q8 x16 fy15_im

9. Selected FFT 16/32 core algorithm (Minimal DSP slices utilization) Basic butterfly computation in a radix-4 FFT algorithm Sixteen-point radix-4 decimation-in-time algorithm

10. XC6VLX240T FPGA utilization

11. Debugging and verification • RTL Matlab model of FFT core , signals values on each pipe line stage • Xilinx simulator • Xilinx development board verification using chip scope • Quantization error estimation against Matlab double precision FFT • Maximal frequency operation validation .

12. To PC Xilinx development board design validation ChipScope FFT 16 points FFT results memory Stimulus ROM Matlab results comarement Data path Data path Input data Control logic Output data control logic PLL Frequency multiplier Increased clock To all modules Input clock

13. FFT 16/32 core design validation and error estimation Results verification between Matlab fft function and 32 FFT core running at 320MHz At Xilinx development board Quantization error estimation Imaginary part of Matlab vs FFT core fft

14. FFT 16/32 core xilinx development board demo Wrap around FFT 32/16 core 4 different signals bank A Real data Transform Real data 4 different signals bank B Transform Imag data Imag data Input clock PLL Operational FFT clock Error estimation