Integrated CMOS 18V 240 μ A Charge Pump with Passive Level Shifters

1. Integrated CMOS 18V 240μA Charge Pump with Passive Level Shifters Vratislav MICHAL, Denis COTTIN, Nicolas MARTY and Patrik ARNO STMicroelectronics, 12 rue Jules Horowitz, Grenoble, France vratislav.michal@st.com

2. Motivation – High power density • Structures with low voltage vs. high voltage capacitors wikipedia Dickson charge pump with linear MOSFET in parallel with diode-wired MOSFET. 4-stage (x5 multiplier) • Small area •  Complicated switches driving  well-known active switches structures  low-denisty capacitors X

3. Preferred architecture: dual phase voltage multiplier • Output power is delivered by one of complementary inputs VIN • Only small output capacitor (high-voltage) • Small CMID filters the voltage spikes in the active structure • First node delivered by the DC input voltage

4. Active level shifter solution • Very high output voltage reached in ref [*] • Active switches driving rely on the floating active level shifters • High-voltage floating level shifters are difficult to design [*] A. Emiraet al. “All-pMOS 50-V charge pump using low voltage capacitors,” IEEE Tran. on ind. Electronics, Vol. 60, No. 10, 2013

5. Single cell - Diodes replacement by the active switches • Complementary gate signals generated by the structure • Steady-state reached by the transistor diodes Pelliconi cell

6. Final structure: Passive level shifter • Passive level shifters helps the fast propagation of the driving signals • Act as HP bypass for driving signal and LP link for DC voltage • Fast driving signals prevent energy loss in the charge-pump structure • FEEDFORWARD capacitor considerably increase the output power

7. Final structure: simulation Internal nodes of Fig. 4 charge pump (upper phase). Lower phase is identical with 180° phase shift. The solid lines correspond to the floating nodes ① to ④ , whereas the dashed lines to the DC middle nodes M1-4. Simulation of the internal nodes of the charge pump (upper phase) without passive level shifter (R = 0).

8. Capacitor Area Optimization • Capacitor are dominant silicon area contributor. • Capacitor distribution is not uniformacross CP stages. • Approximate analytical solution known in the literature. • It is impossible to cover all parasitic elements in the analytical capacitor area distribution. [*] A. Emiraet al. “All-pMOS 50-V charge pump using low voltage capacitors,” IEEE Tran. on ind. Electronics, Vol. 60, No. 10, 2013

9. Capacitor Area Optimization (cont’d) • Optimization target: higher output current for given capacitor area CTOT • Set of equation can be written: • Leading to the capacitor parameters: • These equations can be inserted in the capacitor value property

10. Capacitor Area Optimization results • Optimization is parametric simulation, accounting for all dominant parameters of the charge pump: • Target: higher output voltage for given output current: α = 1.7, β = 1.5 and γ = 2. The CP was connected in the open-loop with G_CTRL = 1V. Simulation done in the worst-case corner (CMIN, slow, 120°C with load current 260μA)

11. 18V Output voltage control • Output voltage control is provided via charge control of the main (input) tank capacitor. • Tank capacitor is used in the input voltage doubler. Charging control

12. Conclusion - Results UV photography 160nm CMOS High-voltage isolated NMOS with >20V breakdown voltage Obtained features Feedback control loop