1 / 12

Memory Hierarchy Review: Cache Design and Control Signals

This review covers the key principles of memory hierarchies, cache design, and control signals in computer architecture. It includes topics such as block placement, block replacement, write strategies, cache performance, and control signal subsets.

hbradley
Download Presentation

Memory Hierarchy Review: Cache Design and Control Signals

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Lab#13- Cache Memory Review - HW#11 - Quiz#4 Apr.20, 2005

  2. Review: Memory Hierarchies • Key Principles: • Locality: spatial and temporal • Smaller hardware is faster • Goal: • Keeping more likely used data as “close” to the CPU as possible - Thanks to Prof. Narahari for his class notes on review of memory.

  3. Cache Design • Where can a block be placed in a cache? • How do we know which elements are in cache? • Which block should be replaced on a miss? • What happens on a write?

  4. Block Placement • Direct mapped is not flexible enough: • Fully associative allows any mapping, i.e. all locations must be searched to find the right one – expensive hardware

  5. set 0 set 1 Block Replacement • Direct-Mapped Cache: determined by index • Set/Fully Associative • Random • LRU (Least Recently Used) • Example: For a 2-way set associative cache with a four word total capacity and one word blocks. Compute the hits and misses for LRU replacement with the following word accesses (ignore bytes for this problem): 0, 2, 0, 1, 4, 0, 2, 3, 5, 4 loc 0 loc 1 0

  6. Write Strategy • Write through • The information is written to both the block in the cache and to the block in the lower-level memory. • Write back: • The information is written only to the block in the cache. The modified cache block is written to main memory only when it is replaced. • A dirty bit is kept in the block description area. • Pros and Cons of each? • WT: read misses cannot result in writes • WB: no writes of repeated writes

  7. Cache Performance • Hit rate: • #requests that are hits / #total requests • Cost of memory access • r*C_hit+(1-r)*C_miss • CPI = ideal CPI + average stalls per instruction • Example: • Ideal CPI=1.1, 50% arith/logic, 30% ld/st, 20% control • 10% of memory operations get 50 cycle miss penalty • 1% of instructions get same miss penalty

  8. HW#11

  9. Quiz#4

  10. Control Signals • Control lines can be divided into 5 groups: • IF – NONE • ID – NONE • ALU – RegDst, ALUOp, ALUSrc • MEM – Branch, MemRead, MemWrite • WB – MemtoReg, RegWrite • Group these nine control lines into 3 subsets: • ALUControl, MEMControl, WBControl • Control signals: • generated at ID stage • grouped into three sets • passed to other stages through pipeline registers.

  11. Extend the pipeline registers to include control information

  12. Problem 2:

More Related