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A simulation study of double side silicon strip detector for the GLC intermediate tracker

A simulation study of double side silicon strip detector for the GLC intermediate tracker. S.P. Kim, H.J. Kim*, Y.J. Kwon (Yonsei U) Y.J.Kim, H.B.Park (KNU), B.G.Cheon(SKKU), J.Lee (SNU), J.S.Kang (Korea U.) 6 th ACFA workshop Dec. 15-17, ‘03. Simulation. • The purpose

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A simulation study of double side silicon strip detector for the GLC intermediate tracker

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  1. A simulation study of double side silicon strip detector for the GLC intermediate tracker S.P. Kim, H.J. Kim*, Y.J. Kwon (Yonsei U) Y.J.Kim, H.B.Park (KNU), B.G.Cheon(SKKU), J.Lee (SNU), J.S.Kang (Korea U.) 6th ACFA workshop Dec. 15-17, ‘03

  2. Simulation •The purpose -To find proper conditions for the fabrication process (process simulation) -To find optimized conditions for the electrical characteristics (device simulation) • ISE–TCAD (Linux) -The industry-standard 1D/2D process simulation tool - Simulate etching, deposition, lithography, implantation, diffusion - Output : boundaries of various layers, impurity distribution, r, E, V, I-V, C-V, etc

  3. ISE-TCAD • •GENESISe : framework • DIOS/FLOOPS : process simulator • DIOS : most accurate processor simulator available • DESSIS : device simulator • INSPECT/TECPLOT : visualization tool • MDRAW/DEVISe : device editor • ISExtract : SPICE extraction • EMLAB : Maxwell solver • OptimISE : optimization tool

  4. TCAD_GENESISe9 • GENESISe9 DIOS –process simulator DESSIS-device simulator

  5. DIOS : Layer Editor Layout (MASK) -pattern P stop P stop n+ implant 2D Simulation section

  6. DIOS : Process Flow Editor

  7. DIOS : Process Flow Editor • Example – wafer (substrate) Wafer – N type (phosphorus) (100) 5000Ω·cm

  8. TECPLOT : Visualization tool

  9. Double sided silicon detector (DSSD) readout (Al) n+ side P-stop 5 KΩcm n-type n+ implantation p+ implantation Double metal layer p+ side

  10. P-stop at n-side To localize signals on n-side  Negatively biased MOS structure  Interleaved p strip SiO2 Field plate Al P-stop n+ High resistivity n-bulk p+

  11. p+ implantation Oxidation layer(SiO2) (100) N-type silicon Boron implantation

  12. n+implantation Phosphorus implantation

  13. Boron Active concentration - depth curve SiO2 layer N-type silicon Depth of implantation (um)

  14. Boron concentration – depth curve after annealing Depth of implantation (um)

  15. Phosphorus active concentration - depth curve SiO2 layer N-type silicon Depth ofimplantation (um)

  16. Phosphorus concentration – depth curveafter annealing junction depth ~1.22um Depth of implantation (um)

  17. N-side characteristics Electron density Hole density Electric field Electric potential

  18. Metal contact • Metal layer : for low-resistivity interconnection and for supplying connection possibilities to the outside • Aluminum : excellent electrical conductivity (but, low melting temp.) Metal(Aluminum)

  19. N-side I-V curve current (A) 2 10 voltage (V)

  20. P side process simulation • Wafer thickness 5um 2nd metal Via (SiO2 layer)~5um Wafer (n type) 1st metal No via contact Via contact

  21. P-side characteristics Electron density Hole density Electric field Electric potential

  22. Summary and plan • ISE-TCAD is being used for the process and device simulation of DSSD. • Process simulation shows that our design looks promising. • Precise device simulation device will be done to find realistic performance of DSSD. • 3-D simulation with larger dimension will be performed. • Simulation results will be compared with fabricated DSSD.

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