Tunneling Devices

EE666 – Advanced Semiconductor Devices Tunneling Devices Dane Wheeler April 19, 2005

Outline • Motivation • Band-to-Band Tunneling • Device Proposals • Fabrication Techniques • Notre Dame Devices • Conclusions

Motivation • Scaling: some proposed tunneling field effect transistor (TFET) designs do not suffer from short channel effects • Power Dissipation: TFETs can beat the 60 mV/decade sub-threshold swing of MOSFETs • Design Flexibility: Circuits can be made with fewer devices

human brain in 2012? Obligatory Moore’s Law Reference http://www.intel.com/research/silicon/mooreslaw.htm

What’s so great about a tunneling device? • Lower sub-threshold swing can allow for lower operating voltages to be used • Negative differential resistance (NDR) properties can be exploited to create simpler designs for bi-stable circuits, differential comparators, oscillators, etc. • Leads to chips that consume less power

Tunneling • Tunneling is a quantum mechanical phenomenon with no analog in classical physics • Occurs when an electron passes through a potential barrier without having enough energy to do so

(Esaki) Tunnel Diode (TD) EC EV EF • Simplest tunneling device • Heavily-doped pn junction • Leads to overlap of conduction and valence bands • Carriers are able to tunnel inter-band • Tunneling goes exponentially with tunneling distance • Requires junction to be abrupt

Band-to-Band Tunneling in a Tunnel Diode (c) (e) I (b) (d) V EC (a) EV EF (a) (b) (c) (d) (e)

I V Figures of Merit Peak current 100 kA/cm2 Peak-to-Valley Ratio (PVR)

Bi-stable Configuration V I D1 X D2 X1 X2 V

TD Differential Comparator VCC D3 D4 CK X M3 M4 D1 D2 VOUT VOUT VIN VIN RL RL M1 M2 I1 I2 ITAIL -VEE

Direct vs. Indirect Tunneling Indirect Direct Indirect materials require phonons to tunnel, thus reducing the probability of a tunneling event

Tunnel Current Expressions

G tox ox tSi y S p+ Si n+ Si D x L W BOX Lateral TFET • Proposed by our own Qin Zhang • Can theoretically beat 60 mV/decade sub-threshold swing

Lateral TFET On State Off State

Another Lateral TFET • Proposed by A. Zaslavsky in SOI, although original idea from Shockley • Gate placed on top of depletion region

More about AZ TFET

Double Lateral TFET • Acts as back-to-back TD pair at 0 gate bias • Gate bias of either polarity will break tunneling condition

Fabrication Techniques • As mentioned earlier, heavily-doped, abrupt junctions are needed • Can be obtained using several different methods • Ion implantation • Rapid thermal diffusion • Molecular beam epitaxy • Laser diffusion

Doping by Rapid Thermal Processor Approach: Rapid thermal diffusion Spin-on diffusants 100 mm wafers IC-compatible processes Modular Process Technology RTP-600S

Proximity Rapid Thermal Diffusion

Rapid Thermal Diffusion Transient-enhanced diffusion effects dominate, increasing diffusivity of dopants

Ion Implantation

Simulated Built-in Field

Simulated Band Diagram

First TDs from Rapid Thermal Diffusion

TDs with Oxide Window Process First demonstration of tunnel diodes on high resistivity 1 – 5 kW cm substrates Enables microwave characterization

Conclusions • Tunnel diodes are expected to add another node in the road • Three-terminal tunnel devices could add several nodes at the end of CMOS-scaling • Challenges facing TFETs are more practical than theoretical • Lithography, SOI process optimization

Tunneling Devices