CPE555A: Real-Time Embedded Systems

1. CPE555A:Real-Time Embedded Systems Lecture 5 Ali Zaringhalam Stevens Institute of Technology

2. Outline Timer interrupt Process concept Scheduling Reference: Giorgio C. Buttazzo, Hard Real-Time Computing Systems, Predictable Scheduling Algorithms and Applications Available online in library CS555A – Real-Time Embedded Systems Stevens Institute of Technology 2

3. Timers • Programmable Interval timer (PIT) • Counts down from some value to zero and then triggers an interrupt • The initial timer value is set by writing to a memory-mapped register • It can be configured to trigger repeatedly by HW without software ISR restarting it CS555A – Real-Time Embedded Systems Stevens Institute of Technology

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6. Volatile Keyword Use • An optimizing compiler decides • that no one in the body of the • Program is changing foo. • So it transforms the program • to an infinite loop. • But foo may be a memory-mapped • I/O and may change externally The volatile keyword tells the complier not to optimize this code. Compiler leaves the code unchanged. CS555A – Real-Time Embedded Systems Stevens Institute of Technology

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12. User Mode vs. System (aka Privileged or Kernel) Mode • Operating system kernel executes in the privileged mode • has unrestricted access to all system resources • protects user programs from each other (e.g., memory protection) • protects system against malicious use (all user access to system resources is via system calls) • User programs run in user mode with controlled access to system resources via system calls • Exception handling is done in system mode because unrestricted access is required CS555A – Real-Time Embedded Systems Stevens Institute of Technology

13. The Path Of I/O Transfer Registes ROM STORE Processor RAM LOAD I/O Common Memory & I/O bus • In both programmed I/O & interrupt-driven I/O, the path for data transfer is through the processor registers • For high-performance systems and high-bandwidth I/O peripherals both techniques are inefficient • Alternative: Direct-Memory Access (DMA) removes the processor from the data transfer path • a limited form of multiprocessing (DMA is a specialized processor) Memory-mapped I/O CS555A – Real-Time Embedded Systems Stevens Institute of Technology

14. I/O Using DMA Memory CPU ROM Data transfer • CPU sends device name, address, length and transfer direction to DMA controller (via memory-mapped I/O) • CPU issues start command to DMA controller • DMA controller provides handshake signals to I/O device & memory including addresses • DMA controller interrupts processor when transfer is complete Control RAM Memory-mapped I/O Interface Interface DMA Controller I/O I/O Peripheral I/O Peripheral DMA CS555A – Real-Time Embedded Systems Stevens Institute of Technology

15. Multiprogramming Computers typically don’t really run multiple programs simultaneously, it just looks that way Each process runs to completion, but is interleaved with other processes As a process runs, it may have to wait for things like user input or disk I/O While one process waits, another can run This is multiprogramming CS555A – Real-Time Embedded Systems Stevens Institute of Technology CS555A – Real-Time Embedded Systems Stevens Institute of Technology 15

16. Process Concept An operating system executes a variety of programs In multi-programming, several programs share (multiplex) CPU resources Process – a program in execution in CPU, each with its own “framework” including program counter stack data section code heap allocated memory CS555A – Real-Time Embedded Systems Stevens Institute of Technology CS555A – Real-Time Embedded Systems Stevens Institute of Technology 16

17. Processes in Memory Both processes may be running the same program (i.e., text). Example: two users opening a browser. Each process has its own resources such as stack, heap and CPU state. Process A Process B CS555A – Real-Time Embedded Systems Stevens Institute of Technology CS555A – Real-Time Embedded Systems Stevens Institute of Technology 17

18. Process States As a process executes, it changes state new: The process is newly created ready: The process is waiting to be scheduled in the CPU running: Instructions are being executed waiting: The process is waiting for some event such as I/O completion to occur terminated: The process has finished execution Only a single process can be in the running state in a single-core CPU at any given time. But many processes can be in the other states. CS555A – Real-Time Embedded Systems Stevens Institute of Technology CS555A – Real-Time Embedded Systems Stevens Institute of Technology 18

19. Process Control Block (PCB) Information associated with each process: • Process state • Program counter • CPU registers • CPU scheduling information (e.g. process priority) • Memory-management information (base & bound registers) • Accounting information (e.g., start time, memory usage) • I/O status information CS555A – Real-Time Embedded Systems Stevens Institute of Technology CS555A – Real-Time Embedded Systems Stevens Institute of Technology 19

20. Context Switch The CPU multiplexes process execution by switching processes in and out When the CPU switches to another process, the system must save the state of the old process and load the saved state (i.e., context) for the new process Context-switch time is overhead; the system does no useful work while switching CS555A – Real-Time Embedded Systems Stevens Institute of Technology CS555A – Real-Time Embedded Systems Stevens Institute of Technology 20

21. CPU Switch From Process to Process Overhead of context switching. Nothing useful is done. CS555A – Real-Time Embedded Systems Stevens Institute of Technology CS555A – Real-Time Embedded Systems Stevens Institute of Technology 21

22. Process Scheduling Queues The operating system manages multi-program execution using a number of queues Job queue – set of all processes in the system Ready queue – set of all processes residing in main memory, ready and waiting to execute Device queues – set of processes waiting for an I/O device Processes migrate among the various queues during execution CS555A – Real-Time Embedded Systems Stevens Institute of Technology CS555A – Real-Time Embedded Systems Stevens Institute of Technology 22

23. Ready Queue And Various I/O Device Queues CS555A – Real-Time Embedded Systems Stevens Institute of Technology CS555A – Real-Time Embedded Systems Stevens Institute of Technology 23

24. Scheduling Concepts Typically there are more processes than processors Scheduling is the issue of ordering the use of system resources for concurrent programs in order to meet some well-defined objectives (e.g. meeting deadlines) Scheduling decisions Allocation/assignment: which processor/core should execute the task Ordering: the order of task execution (e.g., when there is dependency) Timing/dispatching: when the task must execute activation termination dispatching execution preemption CS555A – Real-Time Embedded Systems Stevens Institute of Technology CS555A – Real-Time Embedded Systems Stevens Institute of Technology 24

25. Scheduler Categories Static schedulers make all three decisions at design time May be implemented as part of the compiler May design to avoid critical section issues altogether by timing thread execution Difficult to realize: execution time typically depends on data input which may vary at run-time and cannot be anticipated at design time Dynamic scheduler Performs all three decisions at run-time when a processor becomes available Scheduling unit is typically a thread or process CS555A – Real-Time Embedded Systems Stevens Institute of Technology CS555A – Real-Time Embedded Systems Stevens Institute of Technology 25

26. Preemption Dynamic schedulers typically support preemption Each task has an assigned priority When a higher-priority task is ready to run, the current lower-priority running task is suspended and the higher-priority task is dispatched to the CPU The higher-priority task could be A newly-arrived task Or an interrupt that must be handled CS555A – Real-Time Embedded Systems Stevens Institute of Technology CS555A – Real-Time Embedded Systems Stevens Institute of Technology 26

27. Scheduling With No Preemption Each task runs to completion before the next task is scheduled CS555A – Real-Time Embedded Systems Stevens Institute of Technology CS555A – Real-Time Embedded Systems Stevens Institute of Technology 27

28. Scheduling With Preemption A task can be executed in disjointed intervals assigned by the scheduler based on priority Example: P(J3) > P(J2) > P(J1) CS555A – Real-Time Embedded Systems Stevens Institute of Technology CS555A – Real-Time Embedded Systems Stevens Institute of Technology 28

29. Task Categories & Deadline Hard: A real-time task is said to be hard if missing its deadline may cause catastrophic consequences on the system under control. Nuclear core shutdown Firm: A real-time task is said to be firm if missing its deadline does not cause any damage to the system, but the output has no value. A monitored event (e.g., fire) is reported late Soft: A real-time task is said to be soft if missing its deadline has still some utility for the system, although causing a performance degradation. Switching from active to standby blade later than required CS555A – Real-Time Embedded Systems Stevens Institute of Technology CS555A – Real-Time Embedded Systems Stevens Institute of Technology 29

30. Timing Definitions Arrival timeaiis the time at which a task becomes ready for execution; aka request timeor release time ri Computation timeCiis the worst-case time necessary for the processor to execute the task without interruption Absolute Deadlinedi is the time before which a task should be completed to avoid damage to the system Relative DeadlineDiis the difference between the absolute deadline and the request time Di = di − ri /ri CS555A – Real-Time Embedded Systems Stevens Institute of Technology CS555A – Real-Time Embedded Systems Stevens Institute of Technology 30

31. Timing Definitions - Continued Start timesiis the time at which a task starts its execution Finishing timefi is the time at which a task finishes its execution Response timeRi is the difference between the finishing time and the request time: Ri= fi − ri Lateness: Li= fi −direpresents the delay of a task completion with respect to its deadline; note that if a task completes before the deadline, its lateness is negative Laxityor Slack time: Xi = di − ai − Ciis the maximum time a task can be delayed on its activation to complete by its deadline /ri CS555A – Real-Time Embedded Systems Stevens Institute of Technology CS555A – Real-Time Embedded Systems Stevens Institute of Technology 31

32. Example CS555A – Real-Time Embedded Systems Stevens Institute of Technology CS555A – Real-Time Embedded Systems Stevens Institute of Technology 32

33. Example – Non-preemptive Response Time R1=f1-a1=3-1=2 R2=f2-a2=5-2=3 R3=f3-a3=8-2=6 • Lateness • L1=f1-d1=3-6=-3 • L2=f2-d2=5-5=0 • L3=f3-d3=8-11=-3 3 Deadline Task 2 • Slack Time • X1=d1− a1−C1=3 • X2=d2- a2−C2=1 • X3=d3− a3−C3=6 Deadline 1 Deadline 2 4 10 14 16 0 6 12 8 Time Maximum Lateness = 0 CS555A – Real-Time Embedded Systems Stevens Institute of Technology CS555A – Real-Time Embedded Systems Stevens Institute of Technology 33

34. Example –preemptive Response Time R1=f1-a1=5-1=3 R2=f2-a2=4-2=2 R3=f3-a3=8-2=6 3 • Lateness • L1=f1-d1=5-6=-1 • L2=f2-d2=4-5=-1 • L3=f3-d3=8-11=-3 Deadline Task • Performs better than non-preemptive in terms of maximum lateness. • There can be many feasible schedules with different characteristics. 2 • Slack Time • X1=d1− a1−C1=3 • X2=d2- a2−C2=1 • X3=d3− a3−C3=6 Deadline 1 Deadline 2 4 10 14 16 0 6 12 8 Time Maximum Lateness = -1 CS555A – Real-Time Embedded Systems Stevens Institute of Technology CS555A – Real-Time Embedded Systems Stevens Institute of Technology 34

35. Periodic & Aperiodic Tasks Periodic: infinite sequence of identical activities Activated regularly with period Ti • Aperiodic: infinite sequence of identical activities • With irregular activation CS555A – Real-Time Embedded Systems Stevens Institute of Technology CS555A – Real-Time Embedded Systems Stevens Institute of Technology 35

36. Precedence Constraints The execution of some tasks may depend on the completion of other tasks Precedence graph shows the dependency It must be acyclic Beginning Task: has no predecessor. Ending Task: has no successor. CS555A – Real-Time Embedded Systems Stevens Institute of Technology CS555A – Real-Time Embedded Systems Stevens Institute of Technology 36

37. Resource Constraints Multiple tasks may depend on a single resource (e.g., file, device) for their execution Read/write access must be synchronized for correct execution Shared buffer must be updated atomically (all or none) Shared Buffer Plot is incorrect Y=8 is updated late x=4 is updated but not y=8 CS555A – Real-Time Embedded Systems Stevens Institute of Technology CS555A – Real-Time Embedded Systems Stevens Institute of Technology 37

38. Critical Sections & Mutex Access to the common resource is a critical section Critical sections must be protected via mutual exclusion We will discuss these in later lectures twleaves critical section tw enters critical section CS555A – Real-Time Embedded Systems Stevens Institute of Technology CS555A – Real-Time Embedded Systems Stevens Institute of Technology 38

39. The Scheduling Problem Input A set of n tasks Γ = {τ1, τ2, . . . , τn}, A set of m processors P = {P1, P2, . . . , Pm} A set of s types of resources R = {R1,R2, . . . , Rs} Constraints: timing (deadline), precedence Output Assigning processors from P and resources from R to tasks from Γ in order to complete all tasks under the specified constraints This problem, in its general form, has been shown to be computationally intractable To make the problem of constructing feasible schedules tractable, certain assumptions are made CS555A – Real-Time Embedded Systems Stevens Institute of Technology 39

40. Scheduling Classification - 1 Preemptive The running task can be interrupted at any time to assign the processor to another active task, according to a predefined scheduling policy Non-preemptive A task, once started, is executed by the processor until completion. All scheduling decisions are taken when the current task terminates its execution CS555A – Real-Time Embedded Systems Stevens Institute of Technology 40

41. Scheduling Classification - 2 Static Scheduling decisions are based on fixed parameters (e.g. priority), assigned to tasks before their activation Dynamic Scheduling decisions are based on dynamic parameters (e.g. priority) that may change during task execution CS555A – Real-Time Embedded Systems Stevens Institute of Technology 41

42. Scheduling Classification - 3 Off-line The scheduling algorithm is executed on the entire task set before task activation The schedule is stored in a table and later executed by a dispatcher On-line The scheduling decisions are taken at runtime every time a new task enters the system or when a running task terminates CS555A – Real-Time Embedded Systems Stevens Institute of Technology 42

43. Scheduling Classification - 4 Optimal An optimal schedule minimizes some given cost function defined over the task set If there is no cost function, then the only concern is to achieve a feasible schedule An algorithm is said to be optimal with respect to feasibility if it is able to find a feasible schedule, if one exists Heuristic Uses a heuristic approach in taking its scheduling decisions A heuristic algorithm tends toward the optimal schedule, but does not guarantee finding it CS555A – Real-Time Embedded Systems Stevens Institute of Technology 43

44. Guarantee-Based Algorithms A dynamic scheduler with real-time deadline with admission control A new task arrives The task is accepted only if the deadlines of current tasks are unaffected CS555A – Real-Time Embedded Systems Stevens Institute of Technology 44

45. Example Scheduler Metrics CS555A – Real-Time Embedded Systems Stevens Institute of Technology 45

46. Earliest Due Date (EDD) Jackson’s algorithm A set of n aperiodic tasks A single processor Optimization metric Minimizing maximum lateness Lmax=Maxi(fi-di) Designation: 1 | sync | Lmax sync means that tasks arrive “synchronously”, at the same time Each task can have a different computation time and deadline But they all arrive at the same time CS555A – Real-Time Embedded Systems Stevens Institute of Technology 46

47. EDD Algorithm Given a set of n independent tasks, any algorithm that executes the tasks in order of non-decreasing deadlines is optimal with respect to minimizing the maximum lateness Because all tasks arrive at the same time, preemption is not an issue The static priority assigned to each task is the deadline: the shorter the deadline, the higher the priority We can assume that all tasks arrive at t=0 Each task is characterized by computation time and deadline (C,d) No random task arrival. All tasks arrive at the same time. CS555A – Real-Time Embedded Systems Stevens Institute of Technology 47

48. Proof of EDD Suppose there was a non-EDD schedule S. There must be two tasks a and b where a immediately precedes b but da > db. Why? The schedule can be improved to reduce maximum lateness by interchanging a and b No non-EDD schedule can do better in minimizing maximum lateness The complexity of the EDD algorithm is O(nxlogn): the complexity of the sorting algorithm CS555A – Real-Time Embedded Systems Stevens Institute of Technology 48

49. EDD & Non-EDD Schedules Two cases for possible value of L’max: L’max = f’i – di = fj-di <= fj – dj L’max = f’j – dj <= fj – dj The non-EDD Lmax = fj-dj So in both cases L’max <= Lmax So EDD is no worst than non-EDD Note that fj=f’i because tasks execute consecutively Non-EDD i finishes earlier but has an earlier deadline than j. In this example both fi-di and fj-dj are negative. EDD • Tasks are scheduled as soon as the CPU is available. • There is no preemption. A task runs to completion. • If the schedule is feasible, all deadlines are met and fi-di is negative for all i. CS555A – Real-Time Embedded Systems Stevens Institute of Technology 49

50. Example 1 J4 has maximum lateness = -1 Queue J2 J4 J3 J5 J1 CS555A – Real-Time Embedded Systems Stevens Institute of Technology Dequeue 50