CompE 460 Real-Time and Embedded Systems

1. CompE 460 Real-Time and Embedded Systems Lecture 5 – Hardware Fundamentals

2. Agenda • Prayer/Thoughts • Team Presentation - Brandon • Some Hardware Fundamentals • Open Collector outputs • Tri-state outputs • Signal Overloading • Circuit Timing Parameters • Buses • Address Maps • Attaching multiple things on a bus • Wait states • Wait Signals • No Handshake • PAL’s/FPGA’s • Watchdog Timer

3. Team Presentation • Schematics

4. Future Memory Technologies • DVRAM (Deja-Vue RAM) • the CPU thinks it has the data before it actually does • PVRAM (Presque-Vue RAM) • the CPU only has to pretend to access RAM to get the data • ODRAM (Oracle at Delphi RAM) • returns data the CPU plans to access next (first data access has to be a NOP). • HRAM (Hearsay RAM) • CPU talks to other CPUs and uses what they all think the data is, instead of accessing the data (which may be different) • 711RAM (Seven-Eleven RAM) • always available, but may be held up during the night shift • ARAM (Audio RAM) • like video RAM, but describes the image verbally instead • MRAM (Mumble RAM) • gumb dortle vrmrgish tord summblum sart groff tuldard snangle gnig

5. What wrong with this? A B C D G E F

6. A B C D G E F PC Systems • What is an interrupt (in computer terms)? • On PC Systems, what are some sources of interrupts? • USB • Keyboard • Disk Drive • Mouse • Network Card • Graphics Card • etc • Now, a big dilemma. On many processors, there is only one low asserted interrupt pin. • How can we hook up multiple interrupts to this one pin?

7. Multiple Interrupts on Same Line Open Collector Outputs - Standard parts drive signals either high or low. Some devices (called open collector devices) drive their signals low or let them float. Vcc Why do we need the pull-up resistor? IC 1 INT’ IC 2 uproc

8. Data Bus With this configuration, what will happen if the SRAM tries to send data to the uproc at the same time as the Flash? Data Bus [d31:d0] uproc SRAM Flash How can we fix this?

9. Tri-State Outputs • Standard parts drive signals either high or low. • Open collector devices drive their signals low or let them float. • Tri-State devices can drive output high, low, or let them float. • Used when you want more than one device to drive an input • The outputs are enabled when the CS lines are true • Sometimes need pullup/down resistor on tristate lines – Why? • Figure 2.16 in text

10. Data Bus CS (or sometime called OE lines) will allow only 1 device to drive the bus at a time. Data Bus [d31:d0] uproc SRAM CS0 CS1 Flash

11. Buses • Simple processor example • Microprocessor – A0 to A15, D0 to D7 • ROM – 32k (15 address lines), 8 bit data • RAM – 32k (15 address lines), 8 bit data

12. D0 A0 D1 D0 A1 A0 D2 ROM D1 A2 A1 D3 D2 : A2 : D3 : : : : OE/ CE/ A14 : D7 CPU : A15 D7 A15 D0 A0 RD/ D1 A1 WR/ D2 Clock RAM A2 D3 : : : : WE/ CE/ OE/ A14 D7 A15 Block Diagram What would the memory map look like for this?

13. Memory Map • ROM • 0x00 to 0x7fff • RAM • 0x8000 to 0xffff 0xFFFF RAM 0x8000 0x7FFF ROM 0x0000

14. How about other devices??? • What about attaching keyboards, LCD’s, network chips, etc. • How can we attach these types of devices to the microprocessor? • What types of IO are available? Memory Mapped IO Isolated I/O space

15. ALE CLK A0L-A15L 74F373 (2) Address Latch AD0-AD7,A8-A15 8088 MPU P0 O0 A1L-A3L CLK O1 P1 CBA 74F138 IO Address Decoder 74F374 Port 0 A0L G2b’ IO/M’ G2a’ A15L O7 P7 G1 Vcc AD0-AD7 MN/MX’ 74F245 Data Bus Transceiver D0-D7 DT/R’ O0 CLK DEN’ O1 74F374 Port 1 WR’ O7 O0 CLK O1 74F374 Port 7 O7 Isolated IO Isolated IO Space has separate spaces for IO and memory

16. A0-A15 A0-A15 P0 O0 A1-A3 CLK O1 P1 CBA IO Address Decoder 74F374 Port 0 A0 BF533 G2b’ G2a’ A15 O7 P7 G1 Vcc D0-D7 MN/MX’ 74F245 Data Bus Transceiver D0-D7 DT/R’ O0 CLK DEN’ O1 74F374 Port 1 WR’ O7 O0 CLK O1 74F374 Port 7 O7 Memory Mapped IO Memory Mapped IO uses the same space for IO and memory

17. PLD/FPGA Data, Address, Cntrl UProc RAM Flash UART … A13 A14 A15 RAMCE FlashCE FPGA or CPLD UARTCE Clk

18. Signal Overloading • What is signal overloading? • Caused by connecting too many input circuits to a single output • Also called Fan-out or loading problem • How can you tell if you have a loading problem? • Data Sheets specify the current a device is able to drive on its output lines • Data Sheets also specify the current a device will typically source on its input lines • How can you solve this? • Figure 2.19 in text

19. There is no such thing as Digital!!! • All signals are really analog • It takes a finite amount of time for a signal to travel from one point to another. High speed digital designers need to understand this • Timing diagrams show actual AC timings including propagation delay. http://emp.byui.edu/FISHERR/All_Classes/Digital/74ls00.pdf

20. Digital Circuit Timing • There is a finite amount of time it takes for digital circuits to actually change state • Ex. 74LS04 Propagation Delay is 15ns (max) A A’ A A’ Something to think about - 800 MHz front side bus has clock period of 1.25 ns - 7404 Inverter gate has propagation delay of 15ns

21. Digital Circuit Timing • There are several key timing characteristics associated with digital circuits • Propagation Delay • Setup Time • Hold Time • Max Clock Frequency • Clock pulse high and low times

22. Propagation Delay • Propagation Delay is the time it takes for the output of the circuit to change after the input has changed. • Depending on technologies (TTL, CMOS, ECL, etc), propagation delay’s of modern IC’s range from <1ns to ~100ns.

23. Setup Time • The setup time is the time interval immediately preceding the active transition of the CLK signal during which the control input must be maintained at the proper level. • If this time is not met, the FF may not respond to the CLK appropriately

24. Hold Time • Hold Time is the time interval immediately following the active transition of the CLK signal during which the synchronous control input must be maintained at the proper level. • If this time is not met, the FF may not respond to the CLK appropriately

25. Clock Frequency Spec’s • Max Frequency (Fmax) - This is the highest frequency that may be applied to the CLK input and still have it trigger reliability • Clock Pulse High (Twh) and Clock Pulse Low (Twl) Times – These are the minimum time duration that the clock signal must remain low before it goes high (Twl) and high before it returns low (Twh)

26. Timings • How can we ensure each device can talk to the microprocessor? • 3 Methods • Wait states – figure 3.6 and 3.7 • Wait signal – figure 3.5 • Buy fast enough parts - $$$

27. Timings Typical Bus Read Cycle T1 T2 T3 Clock A0-An RD’ D0-Dn End of bus cycle uP reads data from bus Memory drives data bus uP drives RD low uP drives Address bus to start bus cycle

28. Timings 2-Wait State Bus Cycle Tw Tw T1 T2 T3 Clock A0-An RD’ D0-Dn End of bus cycle uP reads data from bus Memory drives data bus uP drives RD low uP drives Address bus to start bus cycle

29. Timings Wait Signal Bus Cycle T1 T2 T3 Clock A0-An RD’ D0-Dn WAIT The slow device can assert WAIT as long as it needs, and the uP will wait

30. Backup

31. Watchdog Timer Data, Address Bus and Cntrl CPU Glue logic RST Reset WatchDog Restart What kind of glue logic is this?

32. DMA’s • Direct Memory Access (DMA) • Circuitry that can read/write data to/from an IO device and memory • Independent from processor • Need to have arbitration between DMA and processor

33. DMA Address Bus (rd/ wr/) CPU RAM Data Bus Bus REQ Bus ACK DMA IO DMAREQ

34. DMA Timing DMA Request Bus Request Bus Ack Read Write IO Device drives the data bus DMA drives the data bus D0-Dn A0-An DMA drives IO device address on the bus DMA drives memory device address on the bus